Split-CV (Split Capacitance-Voltage) is the semiconductor metrology technique that quantifies interface state density (Dit) at the insulator-semiconductor interface by measuring capacitance-voltage curves at multiple frequencies and extracting the trap response from the frequency-dependent difference — the primary electrical characterization method for assessing gate oxide quality, where interface trap density directly determines threshold voltage stability, carrier mobility degradation, and ultimately transistor reliability.

What Is Split-CV?

• Definition: Measuring C-V characteristics of MOS capacitors or transistors at both low frequency (quasi-static) and high frequency (typically 1 MHz), where the difference between the two responses reveals the contribution of interface traps that can respond at low frequency but cannot follow high-frequency signals.
• Physical Basis: Interface traps at the semiconductor-insulator boundary have characteristic response times — traps near the band edges respond slowly (milliseconds), traps near midgap respond faster (microseconds). Low-frequency measurements capture all traps; high-frequency measurements exclude slow traps.
• Dit Extraction: Interface state density Dit(E) = (1/qA) × [CLF⁻¹ − Cox⁻¹]⁻¹ − [CHF⁻¹ − Cox⁻¹]⁻¹, where CLF and CHF are low- and high-frequency capacitances, Cox is oxide capacitance, q is electron charge, and A is device area.
• Energy Resolution: By sweeping bias voltage, the measurement probes traps at different energy levels within the bandgap — providing an energy-resolved map of interface quality.

Why Split-CV Matters

• Gate Oxide Quality Assessment: Dit > 10¹¹ cm⁻²eV⁻¹ causes measurable Vth instability and mobility degradation — split-CV directly quantifies this critical parameter.
• Process Development Feedback: Every gate oxide process change (oxidation temperature, ambient, post-oxidation anneal) affects Dit — split-CV provides rapid electrical feedback on process quality.
• Mobility Extraction: The split-CV technique simultaneously extracts effective mobility μeff by combining gate capacitance with drain current measurements — essential for MOSFET characterization.
• Reliability Prediction: High Dit correlates with accelerated BTI (Bias Temperature Instability) degradation — split-CV screens for reliability risk early in development.
• Technology Benchmarking: Comparing Dit values across technology nodes, gate dielectrics (SiO₂ vs. HfO₂), and channel materials (Si vs. SiGe vs. III-V) guides material selection.

Split-CV Measurement Methodology

Setup:

• MOS capacitor or MOSFET test structure with known area.
• LCR meter for high-frequency C-V (1 kHz to 1 MHz sweep).
• Quasi-static C-V measurement (slow voltage ramp, measure displacement current).

Low-Frequency (Quasi-Static) C-V:

• Ramp gate voltage slowly (~50 mV/s) and measure displacement current I = C × dV/dt.
• All interface traps respond — captures full trap contribution to capacitance.
• Requires low leakage current (challenging for thin oxides <3 nm).

High-Frequency C-V (1 MHz):

• Standard AC C-V measurement at 1 MHz where slow traps cannot follow the signal.
• Only fast traps (near midgap) contribute to measured capacitance.

Dit Profile Extraction:

• Subtract high-frequency from low-frequency capacitance at each bias point.
• Convert capacitance difference to Dit using standard formulas.
• Map bias voltage to energy position using surface potential models.

Split-CV Quality Benchmarks

Split-CV is the gold standard for semiconductor interface characterization — providing the quantitative electrical measurement that connects gate oxide process conditions to device performance metrics, making it an indispensable tool from early research through production monitoring at every technology node.