Split Lot is a controlled experimental methodology in semiconductor manufacturing where a single production lot of wafers is physically divided into two or more sub-groups, each receiving different process conditions at a specific step, then continuing together through all remaining downstream steps — the gold standard for establishing causal relationships between process variables and outcomes because the shared starting material and shared downstream processing cancel out confounding variation, isolating the effect of the single changed variable.

What Is a Split Lot?

• Definition: A split lot takes a standard 25-wafer lot (or 13-wafer lot on 300 mm) and assigns wafers to different experimental conditions at one or more process steps. The key requirement is that all sub-groups are processed identically at every other step — only the variable under investigation differs.
• Standard Design: Wafers 1–12 receive Recipe A (Process of Record — POR). Wafers 13–25 receive Recipe B (experimental condition). Both groups continue together through all subsequent steps, experiencing identical etch, deposition, lithography, and cleaning conditions.
• Merge Logic: After the split step, wafers are physically recombined into a single FOUP and processed as one lot through all downstream operations. The MES tracks which wafers received which recipe, enabling comparison at electrical test and reliability evaluation.

Why Split Lots Matter

• Causal Proof: Unlike correlation studies that analyze historical data (which are confounded by hundreds of co-varying factors), split lots establish direct causation — if Group B has 5% higher yield than Group A and the only difference was the etch recipe, then the etch recipe caused the yield improvement.
• Noise Cancellation: Because both groups come from the same crystal ingot, the same polishing lot, and the same upstream process history, wafer-to-wafer variation in starting material quality, film thickness, and doping concentration is randomized equally across both groups. This eliminates the confounding that makes historical data analysis unreliable.
• Statistical Power: By controlling for all other variables, split lots achieve statistical significance with far fewer wafers than observational studies. A 12-vs-13 wafer split can detect a 2% yield difference with 95% confidence, whereas detecting the same difference from production data might require thousands of wafers and months of accumulation.
• Cost Efficiency: Running the experiment within a normal production lot minimizes disruption to the factory. The experimental wafers travel through the fab at normal priority, consuming only the marginal cost of the extra recipe setup at the split step.

Split Lot Execution

Step 1 — Experiment Design: Engineer defines the variable, the levels (POR vs. experimental), the wafer assignment, and the response metrics (yield, parametric means, reliability indicators).

Step 2 — Segregation: At the split step, the lot is physically split using a wafer sorter. Wafers assigned to each condition are sorted into separate FOUPs and routed to the appropriate tool/recipe.

Step 3 — Processing: Each sub-group receives its designated recipe. The MES enforces the correct recipe by checking wafer ID against the experiment assignment table.

Step 4 — Merge: After the split step completes, wafers are sorted back into a single FOUP and released to continue as one lot through the remaining process flow.

Step 5 — Analysis: At electrical test (wafer probe), results are analyzed by split group. Statistical tests (t-test, ANOVA) determine whether the experimental condition produced a significant difference.

Split Lot is the scientific method in a semiconductor box — running control and experiment simultaneously on siblings from the same silicon family to prove causality rather than guessing from noisy historical data.