<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">The 6T SRAM cell: two inverters that hold one bit by fighting each other</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Cross-coupled inverters latch the bit; two access transistors let the bitlines read or write it</text><!-- Panel 1: schematic --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; Six transistors</text><text x="32" y="106" fill="#8b949e" font-size="10.5">a latch plus two gates</text><rect x="42" y="118" width="182" height="200" rx="3" fill="#111a24" stroke="#30363d"/><!-- wordline --><line x1="52" y1="132" x2="214" y2="132" stroke="#e0b13a" stroke-width="2"/><text x="150" y="128" fill="#e0b13a" font-size="8">WL (wordline)</text><!-- bitlines --><line x1="60" y1="140" x2="60" y2="300" stroke="#38bdf8" stroke-width="1.5"/><text x="46" y="312" fill="#38bdf8" font-size="8">BL</text><line x1="206" y1="140" x2="206" y2="300" stroke="#38bdf8" stroke-width="1.5"/><text x="196" y="312" fill="#38bdf8" font-size="8">BL&#772;</text><!-- access transistors --><rect x="70" y="150" width="18" height="14" rx="2" fill="#6b5fb0"/><line x1="60" y1="157" x2="70" y2="157" stroke="#8b949e" stroke-width="1"/><line x1="79" y1="140" x2="79" y2="150" stroke="#e0b13a" stroke-width="1"/><rect x="178" y="150" width="18" height="14" rx="2" fill="#6b5fb0"/><line x1="196" y1="157" x2="206" y2="157" stroke="#8b949e" stroke-width="1"/><line x1="187" y1="140" x2="187" y2="150" stroke="#e0b13a" stroke-width="1"/><text x="60" y="180" fill="#c4b5fd" font-size="7.5">M5</text><text x="188" y="180" fill="#c4b5fd" font-size="7.5">M6</text><!-- inverter A box --><rect x="88" y="196" width="34" height="60" rx="3" fill="#0c141d" stroke="#34d399"/><text x="105" y="222" fill="#34d399" font-size="8" text-anchor="middle">INV</text><text x="105" y="234" fill="#34d399" font-size="8" text-anchor="middle">A</text><!-- inverter B box --><rect x="144" y="196" width="34" height="60" rx="3" fill="#0c141d" stroke="#34d399"/><text x="161" y="222" fill="#34d399" font-size="8" text-anchor="middle">INV</text><text x="161" y="234" fill="#34d399" font-size="8" text-anchor="middle">B</text><!-- cross-couple wires --><line x1="122" y1="208" x2="144" y2="244" stroke="#f0d9b5" stroke-width="1.3"/><line x1="122" y1="244" x2="144" y2="208" stroke="#f0d9b5" stroke-width="1.3"/><!-- storage nodes --><circle cx="88" cy="226" r="3" fill="#f87171"/><text x="70" y="229" fill="#f87171" font-size="7.5">Q</text><circle cx="178" cy="226" r="3" fill="#38bdf8"/><text x="182" y="229" fill="#38bdf8" font-size="7.5">Q&#772;</text><!-- access connect --><line x1="79" y1="164" x2="79" y2="226" stroke="#8b949e" stroke-width="1"/><line x1="79" y1="226" x2="88" y2="226" stroke="#8b949e" stroke-width="1"/><line x1="187" y1="164" x2="187" y2="226" stroke="#8b949e" stroke-width="1"/><line x1="178" y1="226" x2="187" y2="226" stroke="#8b949e" stroke-width="1"/><text x="52" y="278" fill="#8b949e" font-size="7.5">4 latch FETs (M1&#8211;M4) + 2 access (M5,M6)</text><text x="52" y="292" fill="#8b949e" font-size="7.5">Q and Q&#772; always hold opposite values</text><text x="32" y="336" fill="#adb5bd" font-size="9.5">Two inverters wired output-to-input</text><text x="32" y="351" fill="#adb5bd" font-size="9.5">form a latch with two stable states.</text><!-- Panel 2: read/write --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; Read &amp; write</text><text x="279" y="106" fill="#8b949e" font-size="10.5">the wordline opens the door</text><rect x="287" y="118" width="196" height="76" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="134" fill="#34d399" font-size="9.5" font-weight="700">Hold (WL = 0)</text><text x="297" y="150" fill="#8b949e" font-size="8.5">access FETs off; the latch feeds back</text><text x="297" y="163" fill="#8b949e" font-size="8.5">on itself and keeps the bit forever</text><text x="297" y="176" fill="#8b949e" font-size="8.5">&#8212; as long as the cell stays powered.</text><text x="297" y="189" fill="#6f8fb0" font-size="8.5">static: no refresh needed.</text><rect x="287" y="200" width="196" height="70" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="216" fill="#9fd8ef" font-size="9.5" font-weight="700">Read (WL = 1)</text><text x="297" y="232" fill="#8b949e" font-size="8.5">precharge both bitlines high, raise WL;</text><text x="297" y="245" fill="#8b949e" font-size="8.5">the storage node pulls one BL down a</text><text x="297" y="258" fill="#8b949e" font-size="8.5">little; a sense amp resolves the bit.</text><rect x="287" y="276" width="196" height="70" rx="3" fill="#111a24" stroke="#30363d"/><text x="297" y="292" fill="#e0b13a" font-size="9.5" font-weight="700">Write (WL = 1)</text><text x="297" y="308" fill="#8b949e" font-size="8.5">drive the bitlines hard to the new value;</text><text x="297" y="321" fill="#8b949e" font-size="8.5">the access FETs overpower the latch and</text><text x="297" y="334" fill="#8b949e" font-size="8.5">flip Q / Q&#772; to the written state.</text><!-- Panel 3: tradeoffs --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; Why SRAM, and its cost</text><text x="526" y="106" fill="#8b949e" font-size="10.5">fast and stable, but big</text><circle cx="532" cy="126" r="2.4" fill="#34d399"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Fast &amp; static</text><text x="542" y="143" fill="#8b949e" font-size="9">single-cycle access, no refresh &#8212; ideal</text><text x="542" y="156" fill="#8b949e" font-size="9">for caches right next to the cores.</text><circle cx="532" cy="176" r="2.4" fill="#38bdf8"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Six transistors = area</text><text x="542" y="193" fill="#8b949e" font-size="9">far larger per bit than DRAM&#8217;s 1T1C,</text><text x="542" y="206" fill="#8b949e" font-size="9">so capacity is limited &amp; expensive.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Stability margins</text><text x="542" y="243" fill="#8b949e" font-size="9">read must not disturb the bit; sizing</text><text x="542" y="256" fill="#8b949e" font-size="9">ratios set read/write noise margins.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#f87171" font-size="10" font-weight="700">The bitcell sets the SoC</text><text x="536" y="306" fill="#adb5bd" font-size="9">SRAM is often half a modern chip&#8217;s area.</text><text x="536" y="320" fill="#adb5bd" font-size="9">Foundries push a specially-drawn cell to</text><text x="536" y="334" fill="#adb5bd" font-size="9">the density limit each node; it drives</text><text x="536" y="348" fill="#adb5bd" font-size="9">cache size, cost and yield.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Cross-coupled latch</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Two inverters hold Q and Q&#772; &#8212; the</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">bit is stored as a stable state.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Access transistors</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">The wordline gates the bitlines onto</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">the node to read or write.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">Static, not stored charge</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Holds its bit with no refresh &#8212; but</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">at six transistors per bit.</text></svg>

Custom SRAM Bitcell Design is the foundational circuit design discipline focused on optimizing the 6-transistor (6T) memory cell for stability, performance, and density at advanced technology nodes — where read stability, write margin, hold margin, and cell area present tightly coupled design trade-offs that define the memory's yield and performance.

6T SRAM Cell Architecture:

• Cross-Coupled Inverters: two CMOS inverters (NMOS pull-down + PMOS pull-up) connected in positive feedback loop store one bit — bistable latch maintains state as long as supply voltage exceeds minimum retention voltage (VMIN)
• Access Transistors: two NMOS pass-gate transistors connect storage nodes to bit-lines during read/write — gate driven by word-line; access transistor sizing critically balances read and write operations
• Cell Ratio (CR): ratio of pull-down NMOS width to access NMOS width — CR > 1.5 required for read stability (pull-down must overpower access transistor during read to prevent flip)
• Pull-Up Ratio (PR): ratio of access NMOS width to pull-up PMOS width — PR > 1.2 required for writability (access transistor must overpower pull-up PMOS to force new data into cell)

Read Operation and Stability:

• Read Mechanism: word-line assertion connects storage nodes to pre-charged bit-lines through access transistors — cell storing '0' discharges one bit-line through series access-NMOS and pull-down-NMOS, creating differential voltage sensed by sense amplifier
• Read Disturb: during read, the '0' storage node rises from VSS due to voltage divider between access and pull-down transistors — if this voltage exceeds the switching threshold of the feedback inverter, the cell flips (destructive read)
• Static Noise Margin (SNM): measured as the maximum DC noise voltage that the cell can tolerate without flipping during read — graphically determined as the largest square inscribed in the butterfly curve of the cross-coupled inverters
• Read SNM Scaling: SNM degrades with technology scaling due to increased Vt variation (RDF), reduced voltage headroom, and higher leakage — 6T cells at 7 nm and below require assist techniques to maintain acceptable read SNM

Write Operation and Margin:

• Write Mechanism: one bit-line driven low while word-line is asserted — access transistor overpowers the pull-up PMOS to force the '1' node to '0', triggering the cross-coupled latch to flip to the new state
• Write Margin: measured as the minimum bit-line voltage required to flip the cell — insufficient write margin causes write failures where the cell retains its old value
• Write Assist Techniques: negative bit-line voltage (NBL) enhances pass transistor drive; word-line boosting increases access transistor gate overdrive; supply voltage collapse weakens pull-up PMOS — each technique trades reliability margin for improved writability

Scaling Challenges:

• Variability: random dopant fluctuation at sub-10 nm nodes causes Vt variation of 30-50 mV between adjacent transistors — 6-sigma design margin requires cells functional across wide Vt distribution
• Cell Area: drive for smallest possible cell (0.025-0.05 μm² at 5 nm) conflicts with need for larger transistors to maintain margins — cell area directly determines SRAM macro density and chip cost
• Leakage: sub-threshold leakage increases exponentially with scaling — half-select leakage in unaccessed cells on the same word-line or bit-line contributes to power consumption and read/write disturb

Custom SRAM bitcell design is the most critical circuit-level enabler of semiconductor memory density — the bitcell's stability margins, noise immunity, and variability tolerance directly determine the maximum memory capacity achievable at each process node and define the yield structure of the entire chip.