SRAM (static random-access memory) stores each bit in a six-transistor latch that holds its value as long as power is on — no refresh, unlike DRAM. It is the fast, on-die memory used for CPU and GPU caches and register files, and it is increasingly the bottleneck because, unlike logic, the SRAM bitcell has nearly stopped shrinking.\n\nThe 6T cell is two cross-coupled inverters plus two access transistors. The inverters (M1-M4) form a bistable latch: whatever value sits on node Q is reinforced by its complement Q̄, so the bit is 'static.' To read or write, the wordline (WL) turns on the two access transistors (M5, M6), connecting Q and Q̄ to the bitline pair (BL, BL̄). The six-transistor cost per bit is why SRAM is far less dense than DRAM or flash — but it is also why it is the fastest memory and lives right next to the compute.\n\nWhy SRAM stopped scaling. Logic transistors keep shrinking roughly 0.6-0.7x per node, but the SRAM bitcell depends on tightly matched, minimum-size transistors, and at 5/3/2 nm the cell hits limits of random dopant variation, patterning, and read/write margin. So while logic area keeps falling, SRAM area barely improves — the 'SRAM scaling wall.' The consequence: cache consumes a growing fraction of every die, and that is a first-order constraint on AI accelerators, which are hungry for on-chip memory to feed their compute.\n\n| | SRAM | DRAM |\n|---|---|---|\n| Cell | 6 transistors | 1 transistor + 1 capacitor |\n| Refresh | none (static) | required (leaks) |\n| Speed | fastest (sub-ns) | slower |\n| Density | low | high |\n| Use | caches, register files | main memory, HBM |\n\n``svg\n\n``\n\nDensity, stability, and yield trade against each other. A smaller cell is denser but has less read/write margin and worse retention under voltage and temperature swing; because bitcells are tiny and mismatch-sensitive, SRAM yield is often the dominant limiter of SoC manufacturability. Designers push back with assist circuits (negative bitline, wordline boost), redundant rows/columns with repair, and larger high-margin cells for critical arrays — spending area to buy stability and yield.\n\nRead SRAM through a quant lens rather than a checkbox-of-memory lens: the numbers that bind are bytes of cache per mm² and the bandwidth that cache feeds the compute. Because the bitcell no longer shrinks with logic, every extra megabyte of on-die SRAM costs real area, so the design question is how much cache actually moves a workload up its roofline — a measured area-versus-bandwidth trade, not a free scaling assumption.