Staining (Defect Delineation) is a wet-chemical or electrochemical technique that creates optical contrast between semiconductor regions of different doping type, concentration, or crystal quality by selectively decorating or etching those regions at different rates. Staining transforms invisible electrical or structural variations into visible features observable under optical or electron microscopy.

Why Defect Staining Matters in Semiconductor Manufacturing: Staining provides rapid, whole-wafer visualization of junction profiles, doping distributions, and crystal defects without requiring expensive or time-consuming electrical measurements.

• Junction delineation — HF-based or copper-sulfate stains differentiate p-type from n-type silicon by depositing copper preferentially on p-type regions, revealing junction depths and lateral diffusion profiles • Doping concentration mapping — Etch rate varies with carrier concentration; dilute HF:HNO₃:CH₃COOH (Dash etch, Secco etch, Wright etch) creates surface relief proportional to doping level • Crystal defect revelation — Preferential etchants (Secco: K₂Cr₂O₇/HF, Sirtl: CrO₃/HF, Wright) create characteristic etch pits at dislocation sites, stacking faults, and slip lines • Rapid turnaround — Staining provides results in minutes versus hours for SIMS or spreading resistance profiling, making it ideal for in-line process monitoring • Cross-section analysis — Applied to cleaved or polished cross-sections to reveal layer structures, well depths, and retrograde profiles in bipolar and CMOS devices

Defect staining remains one of the fastest and most cost-effective techniques for visualizing doping profiles, junction geometries, and crystal defects across entire wafer cross-sections in semiconductor process development.