Static Noise Analysis (SNA) is the technique for verifying that noise on internal chip signals does not cause functional failures — analyzing whether signal disturbances from coupling crosstalk, power supply noise, and leakage currents can generate glitches that propagate through combinational logic to reach and corrupt flip-flop inputs, potentially causing the chip to produce wrong results.

Noise Sources on Chip

How Noise Causes Failures

1. Aggressor wire switches → coupled noise appears on victim wire. 2. Noise pulse enters combinational logic gates. 3. Each gate either attenuates the noise (below switching threshold) or propagates it. 4. If noise reaches a flip-flop setup/hold window → wrong value captured → functional failure.

Static Noise Analysis Flow

1. Extract parasitics: Coupling capacitances between all wire pairs. 2. Compute noise: For each net, calculate worst-case noise from all aggressors. 3. Propagate through logic: Model each gate's noise rejection/propagation. 4. Check at flip-flops: Compare noise amplitude at FF input to noise margin. 5. Report violations: Nets where noise exceeds margin → potential functional failure.

Noise Metrics

• DC Noise Margin (NM): $NM_H = V_{OH} - V_{IH}$, $NM_L = V_{IL} - V_{OL}$.
• Dynamic noise immunity: How wide a pulse a gate can absorb without propagating.
• Noise bump: Maximum voltage disturbance at each net due to coupling.
• Propagated noise: Noise amplitude after passing through logic gates.

Timing vs. Noise

• SI-aware STA: Crosstalk DELAYS timing (speeds up or slows down transition) → checked in STA.
• SNA: Crosstalk creates GLITCHES on quiet nets → checked in noise analysis.
• Both analyses needed: Same physical coupling causes both effects.

Noise Prevention

• Wire spacing: Increase space between sensitive nets and aggressors.
• Shielding: Route ground wires between critical signal pairs.
• Net ordering: Route same-direction (same timing) nets adjacent — reduce relative switching.
• Buffer insertion: Buffers on long nets reduce noise accumulation.
• NDR (Non-Default Rules): Critical nets routed with wider spacing.

Static noise analysis is an essential signoff check for high-reliability chips — a noise-induced glitch that causes a single bit flip in a processor can corrupt data, crash a system, or cause a safety-critical failure, making systematic noise verification as important as timing verification for chip correctness.