Supply Chain for Chiplets is the multi-vendor ecosystem of design houses, foundries, packaging providers, and test facilities that must coordinate to produce multi-die semiconductor packages — requiring unprecedented supply chain complexity where chiplets from different foundries (TSMC 3nm compute, SK Hynix HBM, GlobalFoundries 14nm I/O) converge at an advanced packaging facility (TSMC CoWoS, Intel EMIB, ASE/Amkor) for assembly into a single product, creating new challenges in logistics, quality management, inventory planning, and intellectual property protection.
What Is the Chiplet Supply Chain?
- Definition: The network of companies and facilities involved in designing, fabricating, testing, and assembling chiplets into multi-die packages — spanning IP providers, EDA tool vendors, multiple foundries, memory manufacturers, substrate suppliers, OSAT (Outsourced Semiconductor Assembly and Test) providers, and the final system integrator.
- Multi-Foundry Reality: A single chiplet-based product may require dies from 3-5 different fabrication sources — TSMC for leading-edge compute, Samsung or SK Hynix for HBM, GlobalFoundries or UMC for mature-node I/O, and specialized foundries for RF or photonic chiplets.
- Convergence Point: All chiplets must converge at the packaging facility at the right time, in the right quantity, and at the right quality level — any supply disruption in one chiplet blocks the entire package assembly line.
- Quality Chain: Each chiplet must meet KGD (Known Good Die) quality standards before assembly — the packaging house must trust that incoming chiplets from multiple vendors all meet the agreed specifications.
Why the Chiplet Supply Chain Matters
- Single Points of Failure: If one chiplet is supply-constrained, the entire product is constrained — NVIDIA's GPU production has been limited by HBM supply from SK Hynix and Samsung, and by CoWoS packaging capacity at TSMC, demonstrating how chiplet supply chains create new bottlenecks.
- Inventory Complexity: Multi-chiplet products require managing inventory of 3-8 different die types that must be available simultaneously — compared to monolithic products that need only one die type plus packaging materials.
- IP Protection: Chiplets from different vendors may need to be assembled at a third-party packaging facility — requiring trust frameworks, NDAs, and physical security measures to protect each company's intellectual property during the assembly process.
- Quality Attribution: When a multi-die package fails, determining which chiplet or which assembly step caused the failure requires sophisticated failure analysis — quality responsibility must be clearly defined across the supply chain.
Chiplet Supply Chain Structure
- Tier 1 — Chiplet Design: Companies that design chiplets — AMD (compute), Broadcom (SerDes), Marvell (networking), or custom ASIC design houses. Each chiplet has its own design cycle, verification flow, and tape-out schedule.
- Tier 2 — Chiplet Fabrication: Foundries that manufacture chiplets — TSMC (leading-edge logic), Samsung (logic + HBM), SK Hynix (HBM), GlobalFoundries (mature nodes), Intel Foundry Services. Each foundry has its own process technology, yield learning curve, and capacity constraints.
- Tier 3 — KGD Testing: Test facilities that verify chiplet functionality before assembly — may be the foundry's own test floor, the design company's test facility, or a third-party test house. KGD quality directly determines package yield.
- Tier 4 — Advanced Packaging: Facilities that assemble chiplets into multi-die packages — TSMC (CoWoS, InFO, SoIC), Intel (EMIB, Foveros), ASE, Amkor, JCET. This is currently the most capacity-constrained tier.
- Tier 5 — System Integration: Final assembly of packaged chips into systems — server OEMs (Dell, HPE, Supermicro), cloud providers (AWS, Google, Microsoft), or consumer electronics companies (Apple, Samsung).
Supply Chain Challenges
| Challenge | Impact | Mitigation |
|-----------|--------|-----------|
| HBM supply shortage | GPU production limited | Dual-source (SK Hynix + Samsung + Micron) |
| CoWoS capacity | AI chip bottleneck | TSMC capacity expansion, CoWoS-L |
| Multi-vendor coordination | Schedule delays | Long-term supply agreements |
| KGD quality variation | Yield loss at assembly | Incoming quality inspection |
| IP protection | Trust barriers | Secure facilities, legal frameworks |
| Inventory management | Working capital | Just-in-time delivery, buffer stock |
| Failure attribution | Warranty disputes | Clear quality specifications |
Real-World Supply Chain Examples
- NVIDIA H100: Compute die (TSMC 4nm) + HBM3 stacks (SK Hynix) + CoWoS interposer (TSMC) + package substrate (Ibiden/Shinko) + final assembly (TSMC/ASE) — at least 5 major supply chain participants.
- AMD EPYC Genoa: CCD chiplets (TSMC 5nm) + IOD (TSMC 6nm) + organic substrate (multiple suppliers) + assembly (ASE/SPIL) — chiplets from two different TSMC process nodes.
- Intel Ponte Vecchio: Compute tiles (Intel 7) + base tiles (TSMC N5) + Xe Link tiles (TSMC N7) + EMIB bridges (Intel) + Foveros assembly (Intel) — tiles from both Intel and TSMC fabs.
The chiplet supply chain is the complex multi-vendor ecosystem that must function seamlessly for the chiplet revolution to succeed — coordinating design houses, multiple foundries, memory manufacturers, packaging providers, and test facilities to deliver the right chiplets at the right time and quality, with supply chain management becoming as critical to chiplet product success as the chip design itself.