Surface Roughness Scattering is the interaction of inversion-layer carriers with the atomic-scale physical irregularities of the semiconductor-insulator interface — the dominant carrier mobility-limiting mechanism in the MOSFET inversion layer under high gate field conditions, where strong electric field confinement forces carriers to travel in a quantum-mechanically thin sheet directly adjacent to the rough oxide interface, causing frequent momentum-randomizing collisions with interface height fluctuations of 2–5 angstroms amplitude.
What Is Surface Roughness Scattering?
The Si/SiO₂ interface is not atomically flat — thermal oxidation creates a disordered interface with random height fluctuations (roughness Δ and lateral correlation length Λ). In the ON state of a MOSFET:
1. Inversion Layer Formation: The gate field pulls electrons (NMOS) to the Si/SiO₂ interface — the inversion charge is confined within ~2–5 nm of the surface.
2. Confinement Pressure: Higher gate voltage (V_GS) → stronger vertical field (E_perp) → tighter carrier confinement → carriers travel even closer to the rough interface.
3. Scattering Events: Carriers 'see' the interface roughness as a fluctuating potential — roughness height variations Δ shift the local subband energy by ΔE = qE_perp × Δ. This fluctuating potential deflects carriers, randomizing their momentum.
The Surface Roughness Mobility Model
The standard TCAD surface roughness mobility component (Lombardi model):
1/μ_sr ∝ E_perp² × (Δ²Λ²) / (m*^(1/2))
Key features:
- Strong E_perp dependence (E²): Mobility degrades quadratically with increasing gate field — the single most dramatic mobility variation with bias in MOSFETs.
- Interface quality dependence (Δ): Root mean square roughness amplitude Δ directly controls scalar scattering strength — reducing Δ by 2× reduces surface roughness scattering by 4×.
- Correlation length (Λ): Longer correlation lengths scatter at smaller k-vector transfers (forward scattering), less effective at momentum randomization than short correlation lengths.
Experimental Mobility Peak Shape Explained
The characteristic shape of MOSFET universal mobility vs. effective field:
- Low E_perp: Impurity scattering dominates (from halo/channel dopants) — mobility rises as E_perp increases (more inversion charge screens impurities).
- Peak: Transition between impurity-dominated and roughness-dominated regimes (~0.3–0.5 MV/cm).
- High E_perp: Surface roughness scattering dominates — mobility falls steeply with E^(-2) behavior.
The entire characteristic mobility curve shape is fully explained by the three-component Matthiessen's Rule model combining phonon + impurity + surface roughness contributions.
Why Surface Roughness Scattering Matters
- Universal Mobility: Silicon MOSFET inversion layer mobility follows a universal scaling with effective field regardless of temperature and doping — this universality is the experimental signature of surface roughness scattering dominance in the high-field regime. All Si/SiO₂ interface devices converge to the same mobility-E curve, proving interface-controlled transport.
- High-K Dielectric Mobility Challenge: Replacing SiO₂ with high-K dielectrics (HfO₂, ZrO₂) was essential for scaling gate capacitance. However, high-K films are inherently rougher than thermal SiO₂ at the atomic scale (Δ_SiO₂ ≈ 0.2 nm, Δ_HfO₂ ≈ 0.4–0.8 nm), causing 2–4× more surface roughness scattering. Additionally, high-K introduces remote phonon scattering. The solution adopted at 45 nm node (Intel Penryn, 2007): keep a thin (~1 nm) thermal SiO₂ interfacial layer between silicon and HfO₂ to maintain a smooth, low-defect-density Si/SiO₂ interface.
- FinFET Sidewall Mobility: FinFET channels conduct primarily along the fin sidewalls, which are defined by shallow trench isolation etch processes. Etch-induced sidewall roughness directly degrades FinFET mobility versus planar MOSFETs with smoother thermal oxidation interfaces. Fin sidewall orientation (current flows along (110) plane for (100) wafers) also changes the effective mass, creating a ±20% mobility difference between sidewall vs. top surface conduction.
- Nanosheet Thickness Uniformity: Gate-all-around nanosheet FETs require ultra-thin (3–6 nm) silicon nanosheets with uniform thickness. Nanosheet thickness variation of ±0.5 nm creates local roughness at the bottom and top interfaces — surface roughness scattering limits nanosheet mobility below bulk values and creates V_th variation across nanosheet arrays.
- Interface Passivation: Hydrogen passivation of Si/SiO₂ interface dangling bonds (forming gas anneal, 425°C in N₂/H₂) and careful oxidation temperature profiles to minimize interfacial stress reduce the interface state density and roughness amplitude simultaneously — surface roughness simulation guides the process window for optimal passivation.
Tools
- Synopsys Sentaurus Device: Lombardi surface mobility model fully parameterized for Si, SiGe, and Ge channels with temperature dependence.
- nextnano: Quantum transport simulation with roughness scattering in nanosheet geometries.
- Silvaco Atlas: MOSFET mobility simulation including surface roughness component.
Surface Roughness Scattering is the atomic friction of the MOS interface — the fundamental coupling between inversion-layer carrier transport and the angstrom-scale topographic imperfections at the semiconductor-oxide boundary that dominates MOSFET channel mobility under normal operating conditions, drives the mobility degradation with gate voltage that limits transistor efficiency, and has driven decades of interface engineering effort from the introduction of High-K dielectrics to the atomic-smoothness requirements for nanosheet channel surfaces.