SYCL and Intel oneAPI (DPC++): Standards-Based GPU Programming — cross-vendor portability and unified shared memory model

SYCL is a Khronos-standardized C++17 abstraction layer enabling cross-vendor GPU programming. Intel's DPC++ (Data Parallel C++) is an LLVM-based SYCL implementation supporting Intel GPUs (Xe-HPC Ponte Vecchio) and NVIDIA GPUs.

SYCL Abstractions and Queue Model

SYCL decouples kernel submission from queue execution: create queue→submit work→depend on events. Kernels express via functor or lambda: queue.submit(& { cgh.parallel_for(...); }). Event-based dependencies enable asynchronous execution and pipelining. Buffers encapsulate host-device data transfer, with accessor scoping (read/write/discard) managing data movement automatically.

Unified Shared Memory (USM)

USM (SYCL 2020) simplifies data management via three pointer types: host (CPU), device (GPU), shared (automatically migrated by OS). Shared pointers enable transparent access from both host and device, eliminating explicit buffer/accessor overhead. Device USM (mandatory device ownership) offers highest performance; shared USM trades performance for programmability. Allocations: sycl::malloc_host/device/shared.

Parallel Constructs

nd_range(global, local) defines work distribution: global total work items, local work group size. Item, group, and sub_group classes expose work item properties (IDs, ranges). Hierarchical parallelism via work groups enables local synchronization (group_barrier). Atomic operations and sub_group reductions provide synchronization primitives.

Intel GPU Support

Intel Xe-HPC (Ponte Vecchio) features 128 Xe cores (subslices), 16 GB HBM per GPU. DPC++ compiles to Intel GPU binaries. OpenMP target offloading and SYCL compete for Intel GPU programming—SYCL emphasizes standards compliance, OpenMP targets legacy code.

Cross-Vendor and CUDA Interoperability

SYCL can interop with native CUDA code: sycl::interop::get_native_handle() extracts CUDA stream/device from SYCL queue, enabling mixed SYCL-CUDA codebases. This enables gradual CUDA→SYCL migration. Educational and portability use cases drive adoption; NVIDIA dominance limits practical impact.