Synthesis and Timing Constraints are the SDC (Synopsys Design Constraints) specifications that define the timing requirements, clock definitions, and timing exceptions for a design — guiding synthesis and STA tools to optimize for the correct targets, where incorrect constraints are the #1 cause of silicon failures because the chip will be built to whatever the constraints specify, right or wrong.
Core SDC Commands
| Command | Purpose | Example |
|---|---|---|
create_clock | Define clock source and period | create_clock -period 2.0 [get_ports clk] |
set_input_delay | Specify when input data arrives relative to clock | set_input_delay 0.5 -clock clk [get_ports data_in] |
set_output_delay | Specify when output data must be stable | set_output_delay 0.3 -clock clk [get_ports data_out] |
set_false_path | Mark path that should not be timed | set_false_path -from [get_clocks clkA] -to [get_clocks clkB] |
set_multicycle_path | Path intentionally takes > 1 cycle | set_multicycle_path 2 -from [get_pins reg_a/Q] |
set_max_delay | Override path delay constraint | set_max_delay 5.0 -from A -to B |
set_clock_uncertainty | Add jitter/margin to clock | set_clock_uncertainty 0.1 [get_clocks clk] |
False Path
- A path that exists structurally but can never be sensitized functionally.
- Example: MUX select and data paths that are mutually exclusive.
- Declaring false path → tool ignores it → doesn't waste effort optimizing an impossible path.
- Danger: Over-constraining (missing a false path) wastes area/power. Under-constraining (false path on a real path) → silicon failure.
Multicycle Path
- Path designed to take N clock cycles instead of 1.
- Common: Slow-changing control signals, data that's captured every other cycle.
set_multicycle_path 2 -setup→ path has 2 clock periods for setup check.set_multicycle_path 1 -hold→ adjust hold check accordingly (usually N-1).- Common bug: Forgetting the hold adjustment → false hold violations or missed real violations.
Clock Domain Crossing (CDC) Constraints
- Paths between asynchronous clocks: set_false_path (synchronizers handle timing).
- Paths between related clocks (same source, different dividers): set_multicycle_path or max_delay.
- CDC constraint errors are the #1 cause of inter-domain timing bugs.
Generated Clocks
- Clocks derived from master clock (dividers, PLLs).
create_generated_clock -source [get_pins pll/clk_out] -divide_by 2 [get_pins div/Q]- Must specify source and relationship → tool calculates correct timing relationship.
Constraint Validation
- Lint checks: SDC lint tools detect common constraint errors (floating clocks, conflicting exceptions).
- Cross-probing: Verify constraints match design intent by reviewing timing reports.
- Coverage: Ensure all paths are constrained — unconstrained paths are invisible to STA.
Synthesis constraints are the contract between the designer and the EDA tools — they encode the designer's timing intent, and any error in constraints will be faithfully implemented in silicon, making constraint quality verification as important as RTL verification for first-silicon success.
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