Systematic Yield Loss is yield loss caused by design-process interactions, pattern-dependent failures, and process marginalities — affecting the SAME die locations on every wafer, these losses are deterministic and repeatable, unlike random defect-driven yield loss.

Systematic Yield Loss Sources

• Design Marginality: Features that are near the edge of the process window — print inconsistently.
• Lithographic Hot Spots: Patterns where OPC is insufficient — dose or focus variations cause failure.
• Layout-Dependent Effects (LDE): Transistor performance varies with proximity to neighbors — systematic parametric variation.
• Pattern-Dependent Etch/CMP: CD and thickness vary systematically with local pattern density.

Why It Matters

• Deterministic: Systematic losses affect EVERY wafer — they don't average out with volume.
• Design Fix Required: Process optimization alone cannot fix design-induced systematic losses — design changes or additional OPC needed.
• Detection: Systematic yield loss is identified by spatial analysis — same die fail on multiple wafers (repeating failure patterns).

Systematic Yield Loss is the design-process gap — deterministic yield losses that occur at the same locations on every wafer due to design or process marginality.