Tape-out is the moment a completed chip layout leaves the design team and becomes a manufacturing order at the foundry.

It is a technical checkpoint and a business commitment. The deliverable is usually GDSII or OASIS data plus sign-off collateral, and after submission the cost of discovering a mistake rises sharply. On advanced nodes, mask sets and engineering cycles can represent millions to more than 100 million dollars of exposure, so tape-out quality is less about ceremony than risk control.

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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Tape-Out — From RTL to GDSII</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">the final handoff: design database shipped to the foundry for mask making and fabrication</text>

  <!-- === MAIN FLOW: Design stages (left to right, top) === -->
  <text x="380" y="74" fill="#e6edf3" font-size="12" font-weight="600" text-anchor="middle">Chip Design Flow → Tape-Out</text>

  <!-- RTL -->
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  <text x="67" y="104" fill="#c4b5fd" font-size="9" text-anchor="middle" font-weight="600">RTL</text>
  <text x="67" y="117" fill="#8b98a5" font-size="7" text-anchor="middle">Verilog/SV</text>

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  <polygon points="120,103 126,106 120,109" fill="#3a5a7a"/>

  <!-- Synthesis -->
  <rect x="128" y="86" width="75" height="40" rx="4" fill="#14261f" stroke="#34d399" stroke-width="1.2"/>
  <text x="165" y="104" fill="#6ee7b7" font-size="9" text-anchor="middle" font-weight="600">Synthesis</text>
  <text x="165" y="117" fill="#8b98a5" font-size="7" text-anchor="middle">→ gate netlist</text>

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  <!-- P&R -->
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  <text x="263" y="100" fill="#93c5fd" font-size="8.5" text-anchor="middle" font-weight="600">Place &amp;</text>
  <text x="263" y="112" fill="#93c5fd" font-size="8.5" text-anchor="middle" font-weight="600">Route</text>
  <text x="263" y="122" fill="#6b7684" font-size="7" text-anchor="middle">physical layout</text>

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  <polygon points="316,103 322,106 316,109" fill="#3a5a7a"/>

  <!-- Sign-off -->
  <rect x="324" y="86" width="90" height="40" rx="4" fill="#2a1a0a" stroke="#f59e0b" stroke-width="1.3"/>
  <text x="369" y="100" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">Sign-Off</text>
  <text x="369" y="115" fill="#8b98a5" font-size="7" text-anchor="middle">timing/power/DRC/</text>
  <text x="369" y="125" fill="#8b98a5" font-size="7" text-anchor="middle">LVS/ERC</text>

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  <polygon points="429,103 435,106 429,109" fill="#3a5a7a"/>

  <!-- GDSII -->
  <rect x="437" y="82" width="85" height="48" rx="5" fill="#2a1a1a" stroke="#f87171" stroke-width="1.5"/>
  <text x="479" y="100" fill="#fca5a5" font-size="10" text-anchor="middle" font-weight="700">GDSII</text>
  <text x="479" y="115" fill="#8b98a5" font-size="7.5" text-anchor="middle">final database</text>
  <text x="479" y="126" fill="#6b7684" font-size="7" text-anchor="middle">(polygon geometry)</text>

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  <!-- Foundry -->
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  <text x="598" y="100" fill="#76b900" font-size="10" text-anchor="middle" font-weight="700">FOUNDRY</text>
  <text x="598" y="115" fill="#8b98a5" font-size="7.5" text-anchor="middle">mask making →</text>
  <text x="598" y="126" fill="#8b98a5" font-size="7.5" text-anchor="middle">wafer fab</text>

  <!-- Tape-out marker -->
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  <text x="535" y="65" fill="#f87171" font-size="9" text-anchor="middle" font-weight="600">TAPE-OUT</text>

  <!-- === MIDDLE LEFT: Sign-off checklist === -->
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  <text x="195" y="160" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Sign-Off Checklist (must ALL pass)</text>

  <text x="50" y="180" fill="#fbbf24" font-size="9" font-weight="600">Timing:</text><text x="105" y="180" fill="#8b98a5" font-size="9">STA clean (setup + hold, all corners)</text>
  <text x="50" y="196" fill="#60a5fa" font-size="9" font-weight="600">Power:</text><text x="100" y="196" fill="#8b98a5" font-size="9">IR drop &lt; 5%, EM clean</text>
  <text x="50" y="212" fill="#34d399" font-size="9" font-weight="600">DRC:</text><text x="85" y="212" fill="#8b98a5" font-size="9">design rule check (0 violations)</text>
  <text x="50" y="228" fill="#c4b5fd" font-size="9" font-weight="600">LVS:</text><text x="85" y="228" fill="#8b98a5" font-size="9">layout vs schematic (match)</text>
  <text x="50" y="244" fill="#f87171" font-size="9" font-weight="600">ERC:</text><text x="85" y="244" fill="#8b98a5" font-size="9">electrical rules (antenna, latchup)</text>
  <text x="50" y="260" fill="#8b98a5" font-size="9" font-weight="600">Formal:</text><text x="100" y="260" fill="#8b98a5" font-size="9">equivalence RTL↔netlist↔layout</text>
  <text x="50" y="276" fill="#8b98a5" font-size="9" font-weight="600">Fill:</text><text x="85" y="276" fill="#8b98a5" font-size="9">metal/poly density fill for CMP</text>
  <text x="50" y="292" fill="#6b7684" font-size="8">one DRC error = potential wafer scrap → no shortcuts</text>

  <!-- === MIDDLE RIGHT: What happens after === -->
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  <text x="552" y="160" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">After Tape-Out</text>

  <text x="395" y="180" fill="#fbbf24" font-size="9">1. Foundry OPC + mask data prep (1-2 weeks)</text>
  <text x="395" y="196" fill="#8b98a5" font-size="9">2. Mask fabrication (2-4 weeks)</text>
  <text x="395" y="212" fill="#8b98a5" font-size="9">3. Wafer fabrication (8-14 weeks)</text>
  <text x="395" y="228" fill="#8b98a5" font-size="9">4. Wafer test / sort</text>
  <text x="395" y="244" fill="#8b98a5" font-size="9">5. Packaging + final test</text>
  <text x="395" y="260" fill="#34d399" font-size="9" font-weight="600">6. First silicon! (bring-up + debug)</text>

  <text x="552" y="282" fill="#6b7684" font-size="8.5" text-anchor="middle">Total: 4-6 months from tape-out to working chip in hand</text>
  <text x="552" y="294" fill="#6b7684" font-size="8" text-anchor="middle">re-spin (if bugs): another 4-6 months + $10-50M mask cost</text>

  <!-- === BOTTOM: Scale + economics === -->
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  <text x="380" y="326" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Tape-Out Economics (2024)</text>

  <text x="120" y="350" fill="#6b7684" font-size="9" text-anchor="middle">28nm</text>
  <text x="120" y="364" fill="#8b98a5" font-size="9" text-anchor="middle">~$5M NRE</text>
  <text x="120" y="376" fill="#6b7684" font-size="8" text-anchor="middle">30 masks</text>

  <text x="250" y="350" fill="#8b98a5" font-size="9" text-anchor="middle">7nm</text>
  <text x="250" y="364" fill="#8b98a5" font-size="9" text-anchor="middle">~$30M NRE</text>
  <text x="250" y="376" fill="#6b7684" font-size="8" text-anchor="middle">60 masks</text>

  <text x="380" y="350" fill="#60a5fa" font-size="9" text-anchor="middle">5nm</text>
  <text x="380" y="364" fill="#60a5fa" font-size="9" text-anchor="middle">~$50M NRE</text>
  <text x="380" y="376" fill="#6b7684" font-size="8" text-anchor="middle">80 masks</text>

  <text x="510" y="350" fill="#c4b5fd" font-size="9" text-anchor="middle">3nm</text>
  <text x="510" y="364" fill="#c4b5fd" font-size="9" text-anchor="middle">~$100M NRE</text>
  <text x="510" y="376" fill="#6b7684" font-size="8" text-anchor="middle">80+ masks</text>

  <text x="640" y="350" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">2nm</text>
  <text x="640" y="364" fill="#fbbf24" font-size="9" text-anchor="middle">~$150M+ NRE</text>
  <text x="640" y="376" fill="#6b7684" font-size="8" text-anchor="middle">80+ masks</text>

  <text x="380" y="398" fill="#8b98a5" font-size="9" text-anchor="middle">NRE = Non-Recurring Engineering (masks + design tools + engineering time)</text>
  <text x="380" y="412" fill="#6b7684" font-size="8.5" text-anchor="middle">Only companies shipping millions of units can justify 3nm+ tape-out cost (Apple, NVIDIA, Qualcomm, AMD)</text>

  <!-- Footer -->
  <text x="380" y="438" fill="#e6edf3" font-size="9.5" text-anchor="middle" font-weight="600">A modern AI chip: 2-3 years RTL-to-tapeout, 500-2000 engineers, millions of lines of Verilog, billions of transistors</text>

  <text x="380" y="462" fill="#6b7684" font-size="11" text-anchor="middle">Tape-out is ship day for silicon — once GDSII leaves, there's no undo. Get it right, or pay $100M to try again.</text>
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The safest tape-out flow is boring by design. Freeze the design, run independent sign-offs, review waivers, archive exact tool versions, generate the final stream-out, and submit only after the project has a named owner for every accepted risk. A clean tape-out does not guarantee first-silicon success, but a sloppy one almost guarantees expensive surprises.