Tapeout is the final milestone in IC design where the completed layout database is released to the foundry for mask manufacturing, marking the transition from design to fabrication. Tapeout checklist: (1) Timing sign-off—all corners and modes meet timing (setup, hold, transition, capacitance); (2) Physical verification—DRC clean (design rules), LVS clean (layout vs. schematic), ERC (electrical rules); (3) IR drop analysis—static and dynamic power grid integrity; (4) Electromigration—current density within limits for reliability; (5) Antenna check—cumulative metal area ratios verified; (6) Fill—dummy metal and poly fill for CMP uniformity; (7) DFT—scan chain connectivity, BIST functionality verified. Output format: GDSII or OASIS file containing all mask layers with polygonal geometries. File size: gigabytes for advanced SoCs (billions of polygons). Pre-tapeout reviews: design review with foundry (DRM/DFM compliance), reliability review, test coverage review. Post-tapeout: foundry performs additional checks (mask rule check, reticle enhancement, OPC verification). Tapeout cost: mask set alone is $5-15M+ at advanced nodes (5nm, 3nm), plus NRE for design—making re-spins extremely expensive. Risk mitigation: extensive verification, emulation/prototyping, engineering change order (ECO) capability for late fixes. Metal-only ECO: change only upper metal layers for bug fixes (faster, cheaper than full re-spin). Tapeout schedule: typically fixed by product launch dates, creating intense pressure on design teams for timing closure and verification completion.