Technology Node Comparison is the analytical process of evaluating and comparing semiconductor manufacturing processes across different foundries and technology generations using objective physical metrics — cutting through marketing-driven node naming (where "3nm" at one foundry may have different density than "4nm" at another) to assess actual transistor density, performance, power efficiency, and cost using standardized measurements like contacted poly pitch, metal pitch, and logic cell density.

What Is Technology Node Comparison?

• Definition: Comparing semiconductor process technologies using measurable physical parameters — transistor dimensions, interconnect pitch, logic density (transistors/mm²), SRAM cell size, and electrical characteristics (speed, leakage, voltage) — rather than relying on the marketing node name that has become increasingly disconnected from actual feature sizes.
• Node Name Inflation: The "nm" in node names (7nm, 5nm, 3nm) no longer corresponds to any physical dimension on the chip — TSMC's "3nm" has a minimum metal pitch of ~21 nm, and Intel's "Intel 4" (formerly 7nm) has similar density to TSMC's 5nm, illustrating why physical metrics are essential for fair comparison.
• Key Physical Metrics: Contacted Poly Pitch (CPP), Minimum Metal Pitch (MMP), fin pitch, gate length, and SRAM cell area provide objective comparison points that are independent of marketing naming conventions.
• Logic Density: Measured in millions of transistors per mm² (MTr/mm²), calculated using a standard cell mix (typically 60% NAND2 + 40% scan flip-flop) — the most widely used single metric for node comparison.

Why Technology Node Comparison Matters

• Foundry Selection: Fabless chip companies (Apple, Qualcomm, NVIDIA, AMD) choose foundries based on actual PPA metrics, not node names — accurate node comparison directly influences multi-billion-dollar foundry contracts.
• Cost-Performance Analysis: A "smaller" node isn't always better — if the density improvement doesn't justify the higher wafer cost, staying on the current node may be more economical. Node comparison quantifies this tradeoff.
• Competitive Intelligence: Understanding competitors' process capabilities reveals their potential product performance — if a competitor has access to a denser node, they can build more capable chips at the same die size.
• Roadmap Planning: Comparing current and projected node capabilities guides long-term product planning — knowing when a target density or performance level will be available determines product launch timing.

Node Comparison Metrics

• Contacted Poly Pitch (CPP): The center-to-center distance between adjacent transistor gates — the primary metric for transistor density in the gate direction. Ranges from 90 nm (7nm-class) to 45-51 nm (2nm-class).
• Minimum Metal Pitch (MMP): The tightest metal interconnect pitch, typically at the M1 or M2 layer — determines wiring density and routing capability. Ranges from 40 nm (7nm-class) to 20 nm (2nm-class).
• Logic Density: Transistors per mm² using standard cell methodology — TSMC N3: ~292 MTr/mm², Intel 18A: ~350 MTr/mm² (projected), Samsung 2nm: ~300 MTr/mm² (projected).
• SRAM Cell Size: The area of a 6T SRAM bit cell — a universal density benchmark because SRAM design is highly optimized and comparable across foundries. Ranges from 0.021 mm² (7nm) to 0.0036 mm² (2nm projected).

Technology node comparison is the objective analysis that separates semiconductor marketing from manufacturing reality — using physical metrics like contacted poly pitch, metal pitch, and logic density to enable fair evaluation of process technologies across foundries and generations, guiding the foundry selection and product planning decisions that shape the semiconductor industry.