Temperature Cycling Overview

Temperature cycling (TC) is a reliability test that repeatedly heats and cools packaged semiconductor devices between extreme temperatures to verify resistance to thermal-mechanical stress caused by material expansion/contraction mismatches.

Test Conditions (JEDEC JESD22-A104)

• Condition B (most common): -55°C to +125°C, 1,000 cycles.
• Condition G: -40°C to +125°C, 1,000 cycles (automotive).
• Condition J: -40°C to +150°C, 1,000 cycles (harsh automotive).
• Ramp Rate: 10-15°C/min between extremes.
• Dwell Time: 10-15 minutes at each extreme to ensure thermal equilibrium.
• One cycle: Cold dwell → ramp to hot → hot dwell → ramp to cold ≈ 30-60 minutes.

Failure Mechanisms

• Solder Joint Fatigue: CTE mismatch between chip (Si: 2.6 ppm/°C), substrate (organic: 15-17 ppm/°C), and PCB (17 ppm/°C) creates cyclic strain on solder joints. Fatigue cracks grow until electrical failure.
• Wire Bond Fatigue: Bond wire flexing from CTE-driven die/package movement causes heel cracking.
• Die Cracking: Thermal stress in thin dies or large die-to-substrate CTE mismatch.
• Delamination: Adhesion failure between mold compound, die, and substrate interfaces.
• Package Cracking: Moisture-induced popcorn cracking if moisture absorbed before reflow.

Acceleration Models

• Coffin-Manson: Nf = C × (ΔT)^(-n), where n ≈ 2-3. Wider temperature range → shorter life.
• Norris-Landzberg: Adds frequency and peak temperature dependence.

TC vs. Thermal Shock

• Temperature Cycling: Moderate ramp rates (10-15°C/min). Tests bulk fatigue.
• Thermal Shock: Instant transition (liquid-to-liquid or two-chamber). Tests extreme stress and adhesion.