Test and packaging turn a completed wafer into a dependable product. Fabrication creates transistors and interconnect, but it does not prove that every die works, connect the die to a system, remove its heat, or protect it from moisture and mechanical stress. The manufacturing flow therefore alternates electrical test with physical assembly: wafer sort identifies usable die, packaging creates power and signal connections, and final test verifies the assembled device across its specified operating range.

The economical objective is not simply maximum test coverage or the smallest package. It is the lowest delivered cost for the required defect level, bandwidth, power integrity, thermal resistance, board area, and lifetime. A cheap package can raise cooling or board cost; an elaborate test can consume more tester time than the escapes it prevents. Engineers co-optimize design-for-test, probe strategy, package architecture, and production limits because each decision changes the others.

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  <text x="480" y="38" fill="#e5edf8" font-size="25" font-weight="700" text-anchor="middle">From wafer to qualified packaged device</text>
  <text x="480" y="64" fill="#93a4b8" font-size="14" text-anchor="middle">Electrical screens and physical assembly form one manufacturing control loop</text>
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    <rect x="224" y="112" width="138" height="74" rx="12" fill="#1c1b2f" stroke="#a78bfa" stroke-width="2"/><text x="293" y="144" fill="#ddd6fe">Singulate</text><text x="293" y="166" fill="#93a4b8" font-size="12">saw or laser</text>
    <rect x="410" y="112" width="138" height="74" rx="12" fill="#10251f" stroke="#34d399" stroke-width="2"/><text x="479" y="144" fill="#a7f3d0">Attach die</text><text x="479" y="166" fill="#93a4b8" font-size="12">substrate + TIM</text>
    <rect x="596" y="112" width="138" height="74" rx="12" fill="#292013" stroke="#fbbf24" stroke-width="2"/><text x="665" y="144" fill="#fde68a">Interconnect</text><text x="665" y="166" fill="#93a4b8" font-size="12">bond or bump</text>
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  <text x="125" y="276" fill="#67e8f9" font-size="16" font-weight="700">Feedback:</text><text x="210" y="276" fill="#cbd5e1" font-size="15">fail signatures → diagnosis → yield learning → revised limits and patterns</text>
  <text x="125" y="305" fill="#93a4b8" font-size="14">Known-good die prevents expensive substrates and companion chiplets from being built around a bad die.</text>
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Wafer sort is the first product-level electrical checkpoint. A probe card lands needles, cantilevers, or MEMS contacts on wafer pads or bumps while automatic test equipment applies power and test patterns. The prober controls alignment, contact force, chuck temperature, and wafer motion. The tester measures continuity, leakage, supply current, timing, memory behavior, analog parameters, and functional responses. Results are stored by wafer and x-y die location in a wafer map, allowing good die to proceed and failures to be assigned diagnostic bins.

Sort must be selective. Long tests cost money because tester channels, probe cards, and seconds of insertion time are scarce. Some specifications cannot be measured accurately before packaging, and high current can damage small probe contacts. Production programs screen inexpensive, high-discrimination items early and reserve package-dependent or thermally demanding measurements for final test. Multi-site testing reduces average time per die, but parallel sites can introduce supply droop, thermal coupling, and resource conflicts that require correlation.

Design-for-test converts internal defects into observable tester outcomes. Scan chains replace difficult sequential state exploration with shift-and-capture operations. Automatic test-pattern generation targets stuck-at and transition faults; memory BIST exercises embedded SRAM with compact algorithms; logic BIST creates pseudorandom patterns and compresses responses. Boundary scan improves board and package connectivity diagnosis. Analog test buses, loopback modes, trim registers, and on-chip monitors expose parameters that would otherwise require costly external access.

Coverage is always tied to a fault model. A reported 99% stuck-at coverage does not mean 99% of all physical defects are detected. Resistive opens, small delay defects, cell-aware transistor defects, bridges, and analog marginality may require additional models or stress conditions. Teams validate pattern quality with diagnosis, silicon learning, and defect-oriented experiments rather than treating one coverage number as universal proof.

Defect level connects yield, test escape, and outgoing quality. If (D_0) is the fraction of shipped units that remain defective, (Y) is incoming yield, and (E) is the probability that test misses a defective unit, a useful first-order estimate is

$$D_0 \approx \frac{(1-Y)E}{Y + (1-Y)E}$$

Multiplying (D_0) by one million gives defective parts per million. The equation explains why a test flow that is adequate on a mature, high-yield process may produce unacceptable escapes during a yield excursion. Guardbands, adaptive test, and continuous bin monitoring make the flow responsive to that changing risk.

Singulation and die preparation begin the physical transformation. Back-grinding may thin the wafer for z-height or thermal requirements. A diamond saw or laser separates die along streets while tape supports them. Cleaning removes particles and residue. Pick-and-place equipment then selects good die using the wafer map. Edge chipping, backside cracks, contamination, and map misalignment can destroy otherwise functional devices, so optical inspection and traceability accompany this stage.

Die attach fixes the silicon to a leadframe, laminate substrate, ceramic, interposer, or another die. Epoxy, solder, sintered silver, or hybrid bonding is selected according to temperature, conductivity, stress, and cost. The attachment layer must be thin and void-controlled for heat flow, yet compliant enough to tolerate different coefficients of thermal expansion. Large die and power devices are particularly sensitive to warpage and attach voids.

Interconnect architecture sets the package’s electrical scale. Wire bonding is flexible and economical, but peripheral pads and wire inductance limit density and high-frequency performance. Flip-chip turns the die face-down and connects area-array bumps to a substrate. Shorter connections improve power delivery and signal bandwidth; underfill redistributes mechanical stress around bumps. Redistribution layers can fan fine die pads to a larger pitch or create fan-out packages without a conventional organic substrate.

At the advanced end, a silicon interposer provides dense links between logic chiplets and high-bandwidth memory. Organic bridges or fine-line substrates offer different cost-density tradeoffs. Three-dimensional stacks shorten links further but complicate known-good-die strategy, power delivery, test access, heat removal, and repair. A package labeled “2.5D” or “3D” is an integrated system whose yield is the product of several die, interfaces, and assembly steps.

For independent component yields (Y_i) and an assembly yield (Y_A), the approximate finished-package yield is

$$Y_{package} = Y_A \prod_{i=1}^{n} Y_i$$

Four chiplets at 95% yield combined with 98% assembly yield give only about 79.8% finished yield before later screens. Known-good-die testing, redundancy, repair, and partition choices are essential economic tools, not merely quality refinements.

Power integrity, signal integrity, and thermal design converge inside the package. Power and ground bumps, planes, vias, and decoupling must keep transient droop within the silicon budget. High-speed channels require controlled impedance, low crosstalk, and well-characterized insertion and return loss. Package extraction feeds resistance, inductance, and capacitance models into chip and board simulations. Simultaneous switching noise can otherwise turn a passing die into a system failure.

Junction temperature is often estimated from dissipated power and a specified thermal resistance. Under the stated boundary condition,

$$T_J = T_A + P\,\theta_{JA}$$

The value of ( heta_{JA}) depends on the test board, airflow, orientation, package, and heat-spreading environment; it is not an intrinsic constant valid in every product. High-power devices use junction-to-case characterization, detailed compact models, and computational fluid dynamics. Thermal interface material, lid flatness, heat-spreader size, hotspot location, and neighboring chiplets can dominate the result.

Encapsulation protects the interconnect without making mechanics disappear. Mold compound, lid seal, underfill, conformal coating, and moisture barriers limit contamination and handling damage. Their elastic modulus, cure shrinkage, glass-transition behavior, and moisture absorption generate stress across temperature cycles. Warpage affects board assembly and bump life. Package qualification therefore includes temperature cycling, highly accelerated temperature and humidity stress, high-temperature storage, preconditioning, mechanical shock, vibration, and board-level tests appropriate to the market.

Final test repeats critical electrical checks after assembly and adds measurements that depend on the finished package: full-speed I/O, calibrated analog performance, thermal response, leakage across temperature, and power-delivery behavior. Fuses or nonvolatile bits may store repair information, oscillator calibration, voltage trim, or product bin. Burn-in is used selectively to accelerate early-life mechanisms when its quality benefit exceeds its time, socket, energy, and yield cost.

Production limits require measurement-system discipline. Tester accuracy, load-board loss, socket contact resistance, instrument settling, and correlation between insertions all consume guardband. Limits should distinguish specification from measurement uncertainty and manufacturing margin. Overly loose limits ship risk; overly tight limits discard good units. Gauge studies, golden units, calibration, repeatability analysis, and tester-to-tester correlation keep the screen stable.

Adaptive test uses earlier measurements and population statistics to choose later conditions or test length. A die near a leakage boundary might receive additional stress, while a clearly centered die can skip redundant measurements. This can reduce cost without weakening quality, but only when algorithms are versioned, auditable, monitored for drift, and prevented from learning away rare safety failures.

Traceability closes the manufacturing loop. Wafer lot, coordinate, assembly lot, substrate lot, equipment, recipe, tester, socket, software revision, and time stamps connect a field return to its process history. Spatial wafer patterns can reveal lithography, implant, contamination, or probe issues. Package-bin excursions can expose attach voids or bond-tool wear. Statistical process control should alert on distribution shifts before a fixed limit produces a large population of failures.

Failure analysis moves from symptom to physical cause through non-destructive inspection, electrical localization, X-ray, acoustic microscopy, thermal emission, laser stimulation, cross-sectioning, and microscopy. The result matters only when it updates a design rule, process control, test pattern, package model, or supplier action. A healthy test-and-packaging operation is a learning system: it prevents known defects, detects unexpected ones, and preserves enough evidence to improve the next wafer and package.