Thermal-Aware Physical Design is the floorplanning and placement methodology that considers heat generation and dissipation during chip layout to prevent thermal hotspots that would trigger frequency throttling or reliability degradation — placing high-power blocks (ALUs, caches, clock distribution) with awareness of their thermal proximity, heat spreading paths, and cooling capabilities, where a 10°C reduction in junction temperature improves electromigration lifetime by 2× and reduces leakage power by 25-30%.

Why Thermal-Aware Design

• Traditional PnR: Optimizes timing and area → may cluster high-power blocks → thermal hotspot.
• Hotspot: Local temperature 20-30°C above die average → triggers throttling → loses 15-30% performance.
• Thermal runaway: Leakage increases with temperature → more leakage → more heat → positive feedback.
• Solution: Spread high-power blocks, interleave with low-power → uniform thermal profile.

Thermal Design Flow

<svg viewBox="0 0 628 93" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="628" height="93" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9"> [Floorplan] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [Power Map] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [Thermal Simulation] </tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9"> [Hotspot Analysis]</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">      </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9">                                                      </tspan><tspan fill="#6e7681">↓</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9">      </tspan><tspan fill="#6e7681">└────────</tspan><tspan fill="#c9d1d9"> [Floorplan Refinement] </tspan><tspan fill="#6e7681">←──</tspan><tspan fill="#c9d1d9"> [Temperature Violations]</tspan></text></g></svg>

1. Initial floorplan based on timing and connectivity. 2. Generate power density map (W/mm²) for each block. 3. Run thermal simulation (finite element or compact model). 4. Identify hotspots (locations exceeding temperature target). 5. Modify floorplan: Move high-power blocks apart, add thermal vias. 6. Iterate until thermal profile is acceptable.

Power Density Across Die

Thermal Floorplanning Strategies

Thermal Simulation Tools

3D IC Thermal Challenges

• Stacked dies: Bottom die surrounded by other dies on 3+ sides → heat trapped.
• Top die: Only escape path upward through TIM + heat sink.
• Bottom die: Temperature can be 15-30°C higher than top die.
• Solutions: Through-silicon thermal vias, inter-die thermal interface materials, microfluidic cooling.

Dark Silicon and Thermal Budget

• At advanced nodes: Cannot power all transistors simultaneously → thermal limit.
• Dark silicon: Fraction of die that must remain idle to stay within thermal envelope.
• 5nm: Up to 60-70% of transistors may be dark at any time.
• Thermal-aware architecture: Design for rotation → different blocks active at different times.

Thermal-aware physical design is the bridge between electrical design and physical thermodynamics that determines real-world chip performance — because the actual operating frequency of a modern processor is limited more by thermal throttling than by circuit timing, thermal optimization during floorplanning and placement has a direct and quantifiable impact on delivered performance, making thermal analysis an integral part of the physical design loop rather than an afterthought.