Thermal oxidation is the foundational process that grows silicon dioxide (SiO₂) on a silicon wafer by exposing it to an oxidizing ambient (O₂ or H₂O vapor) at 700–1200°C — consuming silicon from the substrate surface to form a stoichiometric, electrically excellent oxide. This thermally grown SiO₂ is the reason silicon dominates semiconductor manufacturing: no other semiconductor forms a native oxide with such low interface-trap density ($D_{it}$ < 10¹⁰ cm⁻² eV⁻¹), such high dielectric strength (10–15 MV/cm), and such reliable performance as a gate insulator, isolation layer, and sacrificial mask. Every CMOS chip ever built — from the first 10 µm MOS transistor to today's 2 nm GAA nanosheets — depends on thermal oxidation somewhere in its process flow.

The Deal–Grove model — oxidation kinetics. The oxide thickness $x_{ox}$ as a function of time $t$ follows the linear-parabolic law:

where $A$ and $B$ are temperature- and ambient-dependent constants, and $\tau$ accounts for any initial oxide already present. At short times (thin oxide), growth is reaction-rate limited (linear regime, $x \approx (B/A) \cdot t$) — the oxidant supply at the Si/SiO₂ interface is abundant but the surface reaction is slow. At long times (thick oxide), growth is diffusion-limited (parabolic regime, $x \approx \sqrt{B \cdot t}$) — the oxidant must diffuse through the growing oxide to reach the Si interface, and the flux drops as the oxide thickens.

Dry vs wet oxidation. The two standard oxidation ambients give dramatically different growth rates:

The rate difference comes from H₂O's higher solubility and diffusivity in SiO₂ compared to O₂ — roughly 3× higher oxidant flux at the interface in wet ambient.

Crystal orientation dependence. Silicon oxidizes at different rates depending on surface orientation because the reaction rate is proportional to the density of available Si bonds at the interface:

CMOS uses (100) wafers precisely because the slower oxidation and lower bond density produce the best Si/SiO₂ interface quality (fewest dangling bonds → lowest $D_{it}$).

The Si/SiO₂ interface — why it's extraordinary. When Si oxidizes thermally, the SiO₂ forms by consuming Si at the interface — each Si atom bonds to two oxygen atoms in a continuous amorphous network. The resulting interface has an atomically abrupt transition (~0.5 nm) from crystalline Si to amorphous SiO₂ with remarkably few electrically active defects. After forming-gas anneal (FGA, H₂/N₂ at 400–450°C), remaining dangling bonds are passivated by hydrogen, achieving $D_{it}$ < 5 × 10⁹ cm⁻² eV⁻¹ — a factor of 100–1000× better than any deposited (CVD/ALD) dielectric on silicon.

Volume expansion — the 2.27× rule. Oxidation consumes silicon: for every 1 nm of Si consumed, 2.27 nm of SiO₂ grows. The oxide surface rises above the original Si plane while the Si/SiO₂ interface moves downward into the substrate. For a final oxide thickness $t_{ox}$:

This volume expansion creates compressive stress in the oxide (up to 300 MPa for thick films), which retards further growth — the "stress-dependent oxidation" effect significant in narrow features like LOCOS bird's beak and shallow-trench-isolation (STI) corners.

Applications in a modern CMOS flow:

• Gate oxide (now replaced by high-k at ≤45 nm, but still used as interfacial layer): 0.5–1.5 nm thermal SiO₂ grown under the HfO₂ high-k gate stack to maintain interface quality while the high-k provides the capacitance.
• STI liner oxide: 3–10 nm thermal oxide grown on the trench sidewalls before fill — heals etch damage and provides a high-quality isolation interface.
• Pad oxide / screen oxide: 5–15 nm grown before ion implantation to protect the Si surface and scatter implanted ions for more uniform doping.
• Sacrificial oxide: grown and then stripped (in HF) to remove surface damage from prior process steps — consumes the damaged surface layer.
• LOCOS / field oxide (legacy): 200–500 nm wet oxide grown selectively to isolate transistors in older technologies.
• Tunnel oxide (flash memory): 7–9 nm high-quality dry oxide through which electrons tunnel during program/erase in NAND and NOR flash cells.

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  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">Detailed Domain Pipeline, Architectural Blocks &amp; Engineering Performance Optimization (ID 11701)</text>
  
  
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Thermal oxidation in the high-k era. Although high-k dielectrics (HfO₂) replaced SiO₂ as the primary gate insulator at 45 nm, thermal oxidation didn't disappear — it became more controlled. A 0.5–1 nm "interfacial layer" (IL) of thermal SiO₂ is intentionally grown between the Si channel and the HfO₂ gate stack. This IL is essential: it preserves the atomically clean Si/SiO₂ interface that gives low $D_{it}$ and high carrier mobility, while the high-k layer on top provides the capacitance equivalent of a much thinner pure SiO₂ gate. At 3 nm GAA nodes, controlling this IL thickness to ±0.1 nm across the wafer — and around all four sides of each nanosheet — is one of the tightest uniformity specs in the entire process flow.