Thin Film Stress is the mechanical stress stored in deposited films due to lattice mismatch, thermal expansion differences, or growth kinetics — causing wafer bow, film cracking, delamination, and transistor performance changes in semiconductor fabrication.

Sources of Film Stress

Intrinsic Stress (Growth-Induced):

• Arises from film microstructure during deposition.
• Columnar grain growth creates tensile stress (grains pull together).
• High adatom mobility (high T or low rate) → compressive stress.
• CVD, PVD, ALD films all have characteristic intrinsic stresses.

Thermal Stress (Mismatch-Induced):

• $\sigma_{thermal} = E \cdot (\alpha_{film} - \alpha_{substrate}) \cdot \Delta T$
• Where $E$ = Young's modulus, $\alpha$ = thermal expansion coefficient.
• SiN: $\alpha = 2.8$ ppm/°C vs. Si: $\alpha = 2.6$ ppm/°C — small mismatch.
• SiO2: $\alpha = 0.5$ ppm/°C — large mismatch, compressive at room temperature.

Stress Values for Common Films

Effects on Wafer and Devices

• Wafer Bow: Film stress causes curvature → affects litho overlay, CMP uniformity.
• Film Cracking: Excessive tensile stress in thick films → network cracks.
• Delamination: Excessive compressive stress → film buckles and peels.
• Stress Engineering: Intentional stress improves carrier mobility — tensile SiN over NMOS boosts electron mobility ~10–20%.

Measurement Methods

• Wafer bow gauge: Capacitive or optical — before/after film deposition.
• Stoney's Equation: $\sigma = \frac{E_{sub} t_{sub}^2}{6(1-\nu_{sub}) t_{film}} \cdot \kappa$
• XRD: Lattice parameter shift maps absolute biaxial stress.

Thin film stress management is a critical process integration challenge — balancing deposition conditions to achieve target stress while preventing wafer distortion or film failure throughout the fabrication flow.