Threading Dislocations are line defects that propagate vertically through mismatched epitaxial layers from the substrate interface to the film surface — they are the primary crystal quality challenge in heteroepitaxy of GaN on silicon and germanium on silicon, creating non-radiative recombination centers in LEDs, leakage paths in transistors, and the dominant yield limiter in all III-V-on-silicon integration.
What Are Threading Dislocations?
- Definition: Dislocation lines that originate at the mismatched heteroepitaxial interface where strain relief misfit dislocations form, and bend upward (thread) through the grown layer to emerge at the film surface, threading through the entire active device region.
- Formation Mechanism: When an epitaxial layer grows beyond its critical thickness, misfit dislocations nucleate at the interface to relieve biaxial strain. The ends of each misfit segment must terminate either at the crystal edge or by bending upward into the film as threading arms — these threading segments propagate through all subsequently grown layers.
- Threading Dislocation Density (TDD): Expressed in dislocations per cm^2, TDD ranges from 10^4 /cm^2 in high-quality GaAs substrates, to 10^8-10^9 /cm^2 in as-grown GaN-on-silicon, and can be reduced to 10^5-10^6 /cm^2 with multiple defect-reduction epitaxial techniques.
- Burgers Vector: Threading dislocations in III-nitrides typically have Burgers vectors of the a-type (1/3 <11-20>), c-type (<0001>), or mixed a+c type — each type produces different electrical activity and different sensitivities to annihilation techniques.
Why Threading Dislocations Matter
- LED Efficiency: Threading dislocations in GaN-based LED active regions act as non-radiative recombination centers — minority carriers generated by electrical injection recombine non-radiatively at dislocation cores, reducing internal quantum efficiency. High TDD limits maximum wall-plug efficiency regardless of active layer quality.
- Transistor Leakage: Threading dislocations in GaN HEMT buffer layers create leakage paths from gate to drain that limit drain breakdown voltage and raise off-state current in power devices — reducing TDD is directly correlated with improving GaN HEMT breakdown and off-state performance.
- Detector Dark Current: In germanium-on-silicon photodetectors for optical communications, threading dislocations increase dark current through generation-recombination, raising noise floor and limiting sensitivity.
- Heterogeneous Integration Scaling: The primary challenge in monolithic III-V-on-silicon integration for post-silicon CMOS is reducing threading dislocation density from the grown-in 10^9 /cm^2 to below 10^6 /cm^2 — the approximate threshold where threading dislocation impacts on FET performance become tolerable.
- Wafer Bow and Stress: High TDD films are often partially relaxed, altering wafer bow and in-plane stress in ways that interact with lithography overlay and create pattern placement errors across the wafer.
How Threading Dislocations Are Reduced
- Aspect Ratio Trapping (ART): Growing III-V semiconductors in narrow oxide-defined trenches forces threading dislocations to intersect the oxide sidewall and terminate before reaching the film top — achieving TDD reduction proportional to the trench aspect ratio.
- Strained Layer Superlattices (SLS): Alternating thin strained and relaxed layers in the buffer stack cause threading dislocations to bend into the interfacial planes and annihilate with opposite-sense dislocations from other segments, progressively reducing TDD with each superlattice period.
- Epitaxial Lateral Overgrowth (ELO): Selective epitaxial growth through oxide mask openings allows the grown crystal to laterally overgrow the mask, with threading dislocations blocked by the mask edges — producing near-dislocation-free wings adjacent to the seed openings.
Threading Dislocations are the vertical crystal flaws that carry the price of lattice mismatch from the heteroepitaxial interface through every active device layer — reducing their density from billions to thousands per square centimeter is the central materials engineering challenge of III-V-on-silicon integration for future high-efficiency LEDs, power transistors, and monolithic photonics.