Through Glass Via TGV Process is a advanced packaging interconnect technology forming conducting vias through glass substrates, enabling direct chip-to-glass electrical contact — fundamental to advanced packaging and heterogeneous integration of photonic and electronic devices.

Glass Selection and Properties

Glass substrates provide unique advantages over silicon: transparency enabling photonic integration, superior electrical insulation (bandgap ~5.5 eV), low thermal expansion coefficient (<10 ppm/K) matching many materials, and superior chemical/moisture resistance compared to organic laminates. Borosilicate glass (Corning Pyrex) and soda-lime glass commonly used; composition affects etch rate and thermal properties. Borosilicate exhibits lower etch rate requiring longer processing, but superior mechanical properties. Thickness typically 200-500 μm for mechanical rigidity; thin glass (<100 μm) enables bendability but increases fragility.

Through-Glass Via Formation

• Lithography: Photoresist or dry-etch hardmask defines via locations; traditional photolithography enables 50 μm minimum resolution; advanced EUV lithography potentially achieving 10 μm features
• Glass Etch Mechanisms: Thermal diffusion etch in molten salts (historically), or plasma-based etching (modern approach); etching creates via cavity through entire glass thickness
• Plasma Etching: Fluorine-based plasma (CF₄, C₄F₈) etches glass containing SiO₂ matrix forming volatile SiF₄ products; typical etch rate 1-5 μm/min depending on plasma conditions
• Etch Rate Uniformity: Aspect ratio (depth/width) increases from 5:1 (50 μm vias in 250 μm glass) to 50:1 (10 μm vias), challenging plasma chemistry to maintain vertical walls

Alkaline Glass Etch Alternative

• Alkaline Process: Potassium hydroxide (KOH) or sodium hydroxide (NaOH) aqueous solutions selectively attack glass: etch rates 1-10 μm/min depending on concentration and temperature
• Selectivity Advantages: Alkaline etch exhibits high selectivity to photoresist hardmask (minimal resist attack), enabling clean via formation
• Anisotropic Etching: KOH exhibits crystal-plane-dependent etching for crystalline materials; however, glass amorphous so etch rate isotropic
• Chemical Waste: Large quantities of aqueous alkaline solution require neutralization and disposal; environmental concerns limit adoption versus plasma processes

Via Metallization and Plating

• Seed Layer Deposition: Sputtered copper or titanium/copper stack (5-20 nm) provides nucleation site for electrochemical plating; critical for uniform electrodeposit thickness
• Barrier Layer: Titanium or tantalum barrier (10-50 nm) prevents copper diffusion into glass potentially creating leakage paths
• Electrochemical Plating (ECP): Copper sulfate electrolyte deposits copper at controlled current density (1-10 A/dm²) filling via to 50-80% full; subsequent plating cycles complete fill
• Via Resistance: Via resistance R = ρL/A determined by copper resistivity (1.7 μΩ-cm), via length (glass thickness), and cross-sectional area; typical via resistance 0.1-1 mΩ acceptable for most applications

TGV Interposer Integration

• Substrate Role: Glass interposer provides mechanical support and electrical interconnection between chiplets (small die) in chiplet packages; multiple chiplets bonded atop glass surface
• Redistribution Layers (RDL): Metal layers on glass surface route signals between via landing pads and chiplet bumps; typical 2-4 metal layers with 10-50 μm pitch
• Passive Integration: Capacitors and resistors embedded in RDL layers reduce board area and improves power delivery
• Thermal Management: Glass interposer thickness and material selection enables efficient heat spreading; direct metal-to-metal contact with backside cooling spreads heat laterally improving thermal performance

Photonic Integration

Glass transparency enables integrated photonic functionality: on-glass optical waveguides, planar light circuits, and photonic interconnects for optical I/O. Waveguides created through: reactive ion etching of glass surface (ridge waveguides), or precise cleaving creating planar structures. TGV copper vias provide electrical connections between photonic components and electronic driver circuits enabling monolithic photonic-electronic integration.

Challenges and Advanced Concepts

• Mechanical Stress: Glass thermal expansion coefficient mismatch with copper creates stress during thermal cycling; stress relief structures and optimized via spacing minimize warping
• Electrical Breakdown: Via-to-via spacing must prevent electrical breakdown across insulating glass; typical spacing >50 μm for 250 V rated devices
• Cost and Manufacturing: Glass processing requires specialized equipment (glass etch chambers, alkaline baths) adding manufacturing cost; future high-volume adoption depends on process simplification
• Hybrid Integration: Combining glass substrates with silicon and organic substrates enables heterogeneous packages leveraging advantages of each material

Closing Summary

Through-glass via technology represents a critical enabling infrastructure for next-generation heterogeneous packaging combining silicon chips with glass optical substrates, achieving unprecedented bandwidth density and thermal performance — positioning glass interposers as essential for advanced chiplet integration and photonic-electronic convergence.