Through-Silicon Via (TSV) Technology is the 3D integration technique that creates vertical electrical connections through the silicon substrate itself — enabling die-to-die stacking with thousands of inter-die connections at pitches as small as 5-10 um, delivering bandwidth densities 10-100x greater than conventional wire bonding or flip-chip bumping for applications like High Bandwidth Memory (HBM) and 3D logic stacking.

Why TSVs Enable True 3D Integration

Conventional chip-to-chip connections (wire bonds, solder bumps) are limited to the die periphery or surface, with pitches >40 um and hundreds to low-thousands of connections. TSVs penetrate through the silicon, allowing connections at any point across the die area at 5-50 um pitch — enabling millions of vertical interconnections between stacked dies.

TSV Fabrication Flow

1. Via Etch (Bosch Process): Deep Reactive Ion Etching (DRIE) using alternating SF6 (etch) and C4F8 (passivation) cycles drills high-aspect-ratio holes through silicon. Typical TSV dimensions: 5-10 um diameter, 50-100 um deep (aspect ratio 5:1 to 10:1 for via-middle; deeper for via-last). 2. Liner Deposition: A thin SiO2 isolation liner (100-500 nm, by PECVD or thermal oxidation) prevents electrical shorts between the copper fill and the silicon substrate. 3. Barrier/Seed Deposition: PVD TaN/Ta barrier + Cu seed layer. Achieving conformal coverage at the bottom of a 10:1 aspect ratio via is extremely challenging — ionized PVD or ALD barrier processes are used. 4. Copper Fill (Electroplating): Bottom-up copper electroplating fills the via from the bottom to prevent void formation. Superfilling additives (accelerators, suppressors, levelers) control the plating rate differentially to achieve void-free fill. This is the most critical step — a single void in a TSV creates an open circuit. 5. CMP and Reveal: Excess copper is removed by CMP. After thinning the wafer from the backside to the target thickness (50-100 um), the TSV copper tips are exposed ("revealed") from the back surface.

Integration Approaches

• Via-First: TSVs fabricated before FEOL transistor processing. Highest thermal budget but requires TSV-compatible transistor processing.
• Via-Middle: TSVs fabricated after FEOL but before BEOL metallization. The most common approach for logic and memory (used in HBM).
• Via-Last: TSVs fabricated after complete BEOL processing, etching through the full metal stack. Simplest integration but largest TSV diameter.

Applications

• HBM (High Bandwidth Memory): 4-16 DRAM dies stacked with >1000 TSVs per die, delivering 256-1024 GB/s bandwidth.
• 3D Logic: Intel Foveros and TSMC SoIC use TSVs to stack logic chiplets.

Through-Silicon Via Technology is the vertical highway system of 3D integration — turning the silicon substrate from a barrier between stacked dies into a three-dimensional wiring fabric that multiplies interconnect density by orders of magnitude.