Timing closure is the process of ensuring all signal paths in a chip design meet their setup and hold timing constraints. A design is "timing closed" when every path has positive slack—it is the most critical and often most time-consuming milestone in physical design.
Key Concepts
Setup time: Data must arrive at a flip-flop input before the clock edge. Setup slack = required_time - arrival_time. Must be ≥ 0. Hold time: Data must remain stable after the clock edge. Hold slack = arrival_time - required_time. Must be ≥ 0. Slack: Timing margin. Positive = meets constraint. Negative = violation (must be fixed). Critical path: The path with the worst (smallest) slack. Determines maximum clock frequency.
Timing Closure Techniques
Cell sizing: Replace cells with faster (larger) or slower (smaller) variants to balance timing and area. Buffer insertion: Add buffers to long nets to reduce delay. Logic restructuring: Re-synthesize critical logic for fewer stages. Useful skew: Intentionally skew clock to borrow time from non-critical paths. Pipeline insertion: Add registers to break long combinational paths (changes architecture).
Signoff Requirements
All corners and modes analyzed (fast/slow/typical process, voltage, temperature). On-chip variation (OCV) and advanced derating (AOCV/POCV) applied. SI (Signal Integrity) effects included—crosstalk can add or subtract delay. Tools: Synopsys PrimeTime, Cadence Tempus for static timing analysis (STA).