Timing Exceptions (False Paths and Multicycle Paths) are the SDC (Synopsys Design Constraints) directives that instruct static timing analysis tools to relax or ignore timing requirements on specific paths — because certain paths are architecturally guaranteed to never be exercised simultaneously (false paths) or have multiple clock cycles available for data propagation (multicycle paths), and without these exceptions, STA would report thousands of spurious violations that block timing closure and waste engineering effort.
Why Timing Exceptions Are Needed
- STA is pessimistic by nature: Checks ALL topological paths, even impossible ones.
- Without exceptions: Tool reports violations on paths that never propagate data in one cycle.
- Over-constraining: Forces the tool to optimize paths that don't matter → wastes area and power.
- Under-constraining (missing exceptions): Hides real timing problems → silicon failure.
False Paths
- Definition: A path that is topologically valid but functionally impossible.
- STA should NOT check timing on false paths.
# Mux select is static during normal operation
set_false_path -from [get_ports test_mode]
# No timing relationship between async clock domains
set_false_path -from [get_clocks clk_a] -to [get_clocks clk_b]
# Static configuration register
set_false_path -from [get_cells config_reg*]
Common False Path Scenarios
| Scenario | Reason | SDC |
|---|---|---|
| Test mode select | Static during functional mode | set_false_path -from test_mode |
| Async clock domains | Handled by CDC synchronizers | set_false_path between clocks |
| Mutually exclusive mux paths | Only one active at a time | set_false_path through mux |
| Static config registers | Written once at boot | set_false_path -from config |
| Reset deassertion | Handled by reset synchronizer | set_false_path on reset |
Multicycle Paths
- Definition: A path where data is valid for more than one clock period.
- STA should allow N clock cycles instead of 1.
# Data path has 2 cycles for setup, capture on 2nd edge
set_multicycle_path 2 -setup -from [get_cells slow_reg*] -to [get_cells dest_reg*]
set_multicycle_path 1 -hold -from [get_cells slow_reg*] -to [get_cells dest_reg*]
Multicycle Path Scenarios
| Scenario | Cycles | Example |
|---|---|---|
| Slow enable register | 2-4 | Data valid every 2 clocks, enable gated |
| Multi-stage pipeline | N | Intentional multi-cycle computation |
| Divided clock logic | 2 | Logic between clk and clk/2 domains |
| Memory write data | 2 | Data setup to SRAM write port |
Multicycle Path Setup/Hold Math
- Default: Setup checked at 1 cycle, hold checked at 0 cycles.
- MCP of N: Setup checked at N cycles, hold should be at (N-1) cycles.
- SDC: set_multicycle_path N -setup → moves setup check to Nth edge.
- SDC: set_multicycle_path (N-1) -hold → moves hold check to (N-1)th edge.
- Forgetting hold adjustment: Common mistake → hold checked at wrong edge → false violations or missed bugs.
Dangers of Exception Misuse
| Mistake | Consequence |
|---|---|
| False path on real path | Silicon timing failure → functional bug |
| MCP on single-cycle path | Data captured wrong → intermittent failure |
| Overly broad wildcards | Accidentally exclude critical paths |
| Stale exceptions after ECO | New paths not covered → missed violations |
Best Practices
- Document every exception with design intent rationale.
- Use CDC tools to auto-generate async false paths.
- Review exceptions after every major design change.
- Use formal property checking to verify false path assumptions.
- Minimize wildcard usage → be specific about path endpoints.
Timing exceptions are the essential bridge between architectural intent and physical implementation — they encode the designer's knowledge of which paths actually matter for correct operation, enabling STA to focus optimization effort where it counts while avoiding the impossible task of meeting timing on paths that the circuit architecture guarantees will never be exercised under normal operation.
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