TiN ALD for Barriers and Electrodes is the deposition of thin titanium nitride films via atomic layer deposition (ALD) from TDMAT or TiCl₄ precursor — serving as diffusion barriers, metal electrodes, and hardmasks — enabling critical process steps in advanced CMOS from 28 nm and below. TiN is indispensable for interconnect and gate integration.
ALD TiN Deposition Chemistry
TiN is deposited via ALD in a cyclic process: (1) TiCl₄ or TDMAT (tetrakis(dimethylamido)titanium) dose pulse, (2) purge with inert gas, (3) NH₃ or N₂ plasma pulse (or H₂ + N₂ plasma), (4) purge. The TDMAT + N₂ plasma path is preferred for lower temperature (100-300°C), while TiCl₄ + NH₃ requires higher temperature (250-400°C). ALD TiN growth rate is ~0.6-1.0 Ångström/cycle, enabling precise thickness control. Conformal coverage is excellent even on high-aspect-ratio features (>10:1).
Diffusion Barrier for Cu and W
TiN serves as a barrier between copper or tungsten interconnects and the underlying dielectric. Cu readily diffuses into oxide at elevated temperature, causing: (1) increased leakage (Cu fills oxide traps, shifts flatband voltage), (2) electromigration acceleration, and (3) reliability degradation. TiN barrier (~20-30 nm thick) blocks Cu diffusion and reduces EM activation energy. Similarly, TiN prevents W reaction with SiO₂ at high temperature (contacts, gate). Barrier thickness is optimized: thin barrier reduces parasitic resistance, thick barrier improves diffusion blocking and EM performance.
Metal Gate Electrode
In gate-last processes, TiN is deposited as the metal gate electrode (work function ~4.9 eV, mid-gap between n+ and p+ Si). Other metals (e.g., TiAlC) are co-sputtered to modulate work function toward desired Vt targets. Dual-metal or quad-metal gate schemes use different metal compositions in n-channel and p-channel devices. TiN ALD provides uniform thickness, low surface roughness (advantageous for gate-first patterning), and excellent coverage of complex topography.
TiN Hardmask for Patterning
TiN is used as a hardmask during photolithography: a thin TiN film is deposited on photoresist, then photoresist is developed. During resist etch, TiN hardens the features; during gate etch, TiN acts as a hard etch stop, protecting gate dielectric from damage. TiN has high selectivity to underlying materials (SiO₂, Si, HfO₂): TiN:HfO₂ etch ratio in Cl₂-based plasma is ~3:1 (TiN faster). TiN hardmask thickness is typically 5-15 nm for this application.
TiN Resistivity and Thickness Dependence
Bulk TiN resistivity is ~100-200 µΩ·cm, roughly 20-40x higher than Cu (1.7 µΩ·cm). However, this is acceptable for barrier layers (thin, <50 nm) where resistance contribution is modest. At very thin thickness (<10 nm), TiN resistivity increases due to grain boundary scattering and surface scattering, reaching 300+ µΩ·cm. For gate electrodes, TiN thickness is 10-30 nm depending on gate resistance targets. Dual-metal schemes use thin TiN (~10 nm) + thicker work-function metal (TiAlC, TaC, ~15-20 nm) to balance resistance and work function.
Nucleation and Substrate Compatibility
TiN ALD nucleates readily on most surfaces (metal, oxide, nitride). However, nucleation delay occurs on some substrates (bare SiO₂ may require pre-treatment). Nucleation delay (first few cycles) produces different film composition (nonstoichiometric TiNₓ). This can degrade barrier performance or change work function. Nucleation is improved by plasma pre-treatment or seeding layers (1-2 nm other material).
ALD vs PVD Comparison
TiN can also be deposited via physical vapor deposition (PVD, sputtering) at lower temperature (room temperature) and higher rate (>1 nm/s). However, PVD provides poor conformality on high-aspect-ratio features (step coverage ~50%) and results in columnar, stress-prone films. ALD is superior for conformal coverage, lower impurities (C, O <1%), and better interface quality. Trade-off: ALD is much slower (nm/min vs nm/s), making throughput-critical applications (thick barriers) prefer PVD.
Impurity Content and Reliability
ALD TiN deposited from TDMAT + N₂ plasma contains oxygen impurity (N/Ti ratio <1 due to incomplete nitrogen incorporation, O/Ti ~0.1-0.2). This deficiency in nitrogen (forming TiNₓOᵧ) affects resistivity and barrier performance. Higher N₂ plasma power or longer plasma pulse improve stoichiometry. Minimizing O is critical for reliability: oxygen in barriers can migrate during thermal stress.
Applications Beyond Barriers and Electrodes
TiN is used as: (1) contact barrier on tungsten via plugs (15-30 nm), (2) metal gate in gate-last RMG (10-30 nm), (3) hardmask during gate etch (~5-15 nm), (4) anti-reflection coating (ARC) in advanced lithography (~20-50 nm), and (5) adhesion layer for Cu or W (10-20 nm). Its versatility stems from conformal deposition, barrier properties, and optical absorption.
Summary
TiN ALD is a cornerstone of advanced CMOS, providing conformal, low-impurity barriers and electrodes essential for sub-7 nm scaling. Continued development in ALD chemistries and work-function modulation will support future node requirements.