Titanium Nitride (TiN) Deposition is the thin-film process that deposits TiN — a refractory, electrically conductive metal nitride — as a barrier layer, gate electrode, work function metal, or hard mask in CMOS manufacturing — serving as one of the most versatile materials in the CMOS process stack. TiN's combination of electrical conductivity (~100 µΩ·cm), hardness (2000 HV), thermal stability (stable to >900°C in silicon), and excellent diffusion barrier properties makes it indispensable in gate stacks, copper interconnects, and DRAM capacitor electrodes.

TiN Properties

TiN Deposition Methods

1. ALD TiN (Atomic Layer Deposition)

• Precursors: TiCl₄ + NH₃ (thermal ALD) or TiCl₄ + plasma N₂/H₂ (PEALD).
• Temperature: 300–400°C (thermal); 200–350°C (plasma-enhanced).
• Conformality: >99% step coverage in high-aspect-ratio features (gate spacers, trench liners).
• Thickness control: 0.05–0.1 nm/cycle → sub-1 nm precision.
• Use: Gate work function metal, barrier liner in contacts, DRAM capacitor electrode.

2. PVD (Sputtering) TiN

• Reactive sputtering: Ti target + N₂/Ar gas → TiN film.
• Deposition rate: 50–200 nm/min (much faster than ALD).
• Step coverage: ~30–50% (limited for deep features).
• Use: Thick TiN layers, flat surfaces, hardmask applications.

3. CVD TiN

• TiCl₄ + NH₃ at 400–600°C → TiN film.
• Better conformality than PVD, faster than ALD.
• Residual Cl can cause device reliability issues → ALD preferred for gate stack.

TiN in HKMG Gate Stack

High-k (HfO₂) → TiN (thin, ~1–3 nm ALD) → other WF metals → W or Ru fill

• TiN work function: ~4.6 eV — near Si midgap → suitable for PMOS or as starting layer for NMOS VT tuning.
• Thickness tuning: Thinner TiN → WF shifts toward n-type (due to interface states); thicker → approaches bulk TiN WF.
• TiAlC capping TiN: Adds Al to lower WF toward 4.1 eV → NMOS LVT.

TiN as Barrier in Copper Interconnect

• Deposited by PEALD in vias and trenches before Cu seed layer.
• Blocks Cu diffusion into low-k dielectric → prevents reliability failure.
• Thickness: 1–3 nm (must be thin to preserve via volume for Cu fill).
• At narrow pitches (10nm half-pitch): TiN barrier resistance dominates total via resistance → switching to Ru or Mn barriers.

TiN as Hard Mask

• PVD TiN (30–60 nm) used as hard mask during gate etch, STI etch, and metal patterning.
• High etch selectivity to photoresist and TEOS oxide → maintains CD through long etch processes.
• Removed by hot H₂O₂ or wet strip after etch → clean removal without damaging underlying materials.

TiN in DRAM

• Used as electrode in MIM (Metal-Insulator-Metal) capacitor: TiN / ZrO₂ / TiN stack.
• ALD TiN provides smooth, pinhole-free electrode → reduces leakage through thin high-k.
• Also: TiN contact plug in DRAM bit-line contacts.

TiN is the semiconductor industry's most versatile thin film — simultaneously serving as work function metal, diffusion barrier, hard mask, and capacitor electrode across CMOS, DRAM, and NAND flash processes, its uniquely balanced combination of conductivity, hardness, stability, and ALD compatibility has made it irreplaceable in every advanced technology node for three decades.