Transmission line. is an interconnect whose distributed inductance and capacitance cause signals to propagate as waves rather than change everywhere simultaneously. The practical trigger is edge transition time compared with interconnect flight time, not clock frequency alone. If a trace delay is a meaningful fraction of rise or fall time, transmission-line analysis is needed even for a low repetition-rate clock. The often quoted wavelength fractions are useful for sinusoidal reasoning, but digital interfaces require edge-rate and channel-budget analysis. Board engineering turns a logical interconnect into manufactured copper, dielectric, plated holes, solder mask, finishes, and assembled components. Requirements must identify voltage, current, edge rate, loss, jitter, temperature, environment, regulatory class, manufacturable feature sizes, inspection access, service life, and acceptable cost. The electrical reference plane is part of every signal path, so a net cannot be judged from its visible trace alone. Stackup, materials, copper roughness, glass weave, via construction, component launch, connector, enclosure, and cables jointly determine behavior.

Physical principles and design constraints. Characteristic impedance Z0 is the ratio of traveling-wave voltage to current and follows per-unit-length inductance, capacitance, resistance, and conductance. Propagation delay depends mainly on effective permittivity. Attenuation combines conductor loss, dielectric loss, radiation, and mode conversion; dispersion changes waveform shape because frequency components travel or attenuate differently. Microstrip fields occupy dielectric and air, making it relatively fast and exposed. Stripline is embedded between planes with stronger shielding. Grounded coplanar waveguide adds nearby ground conductors that can confine fields when stitched correctly. High-speed behavior follows electromagnetic fields rather than an ideal wire model. Return current concentrates near the outbound trace at high frequency because that path minimizes loop inductance; discontinuities force fields to spread and create reflection, mode conversion, crosstalk, and radiation. Resistance includes skin and proximity effects, dielectric loss depends on frequency and material, and copper roughness changes effective path length. Power delivery is also distributed: planes, vias, capacitors, packages, and die form a frequency-dependent impedance network with resonances and antiresonances.

Implementation workflow and manufacturing control. A stackup calculation sets trace width and gap from dielectric height, copper thickness, plating, material properties, and fabrication etch behavior. Solder mask changes surface-line impedance. Differential and common modes see different environments. Bends, neck-downs, pads, vias, anti-pads, reference transitions, plane openings, connectors, and packages receive local models. Lossy-line models replace ideal delay elements for long channels. Copper roughness and dielectric data must match the supplier construction and frequency range; generic FR-4 constants are inadequate for tight multi-gigabit budgets. Implementation begins with an approved stackup and fabrication capability. Constraint classes encode width, spacing, reference layer, impedance, differential gap, length or delay tolerance, via style, neck-down, clearance, and prohibited regions. Placement protects critical current loops before autorouting. Reference changes receive nearby return vias; plane splits are kept away from fast routes; decoupling connects with short, wide paths. Fabrication notes define materials, finished thickness, copper weights, controlled-impedance coupons, via filling, surface finish, solder mask, acceptance criteria, and revision identity.

Applications, alternatives, and system trade-offs. Microstrip is accessible for routing, probing, and component mounting but couples more readily to the environment. Stripline offers shielding and routing density but adds vias and often more dielectric loss. Coplanar structures are useful for RF launches, controlled field confinement, and certain dense surface routes, but ground-gap and via-fence geometry matter. Embedded microstrip, dual stripline, broadside coupling, substrate-integrated waveguide, cable, flex, and package traces extend the same electromagnetic principles to different manufacturing domains. The right construction depends on the product. Dense compute boards emphasize high layer count, low-loss channels, large BGAs, power delivery, and cooling. Automotive controllers add temperature, vibration, moisture, transient, and long-life requirements. RF boards need field-solver-backed launches and material control. Power boards emphasize creepage, clearance, copper current density, thermal spreading, and switching-loop geometry. Cost-sensitive products minimize layers and via processes, but a lower bare-board price can be erased by yield loss, rework, field returns, or excessive validation cycles.

<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif"><rect width="760" height="470" fill="#0d1117"/><defs><marker id="arrow" viewBox="0 0 10 10" refX="8" refY="5" markerWidth="6" markerHeight="6" orient="auto"><path d="M0 0L10 5L0 10Z" fill="#60a5fa"/></marker><marker id="green" viewBox="0 0 10 10" refX="8" refY="5" markerWidth="6" markerHeight="6" orient="auto"><path d="M0 0L10 5L0 10Z" fill="#34d399"/></marker></defs><text x="380" y="34" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Transmission Line — A Wave Sees Distributed L and C</text><text x="380" y="56" fill="#8b98a5" font-size="13" text-anchor="middle">voltage and current propagate with delay, reflect at a mismatch, and settle after round trips</text><g transform="translate(51 111)"><circle cx="34" cy="96" r="31" fill="#10233b" stroke="#60a5fa" stroke-width="2"/><path d="M15 96q10-19 20 0t20 0" fill="none" stroke="#93c5fd" stroke-width="3"/><text x="34" y="145" fill="#93c5fd" font-size="9.5" text-anchor="middle">step source</text><path d="M65 96H621" stroke="#60a5fa" stroke-width="5"/><path d="M65 227H621" stroke="#64748b" stroke-width="5"/><g stroke="#f59e0b" stroke-width="2"><path d="M103 96q12-23 24 0t24 0M213 96q12-23 24 0t24 0M323 96q12-23 24 0t24 0M433 96q12-23 24 0t24 0"/></g><g stroke="#a78bfa" stroke-width="2"><path d="M170 104v42M158 146h24M158 157h24M170 157v70M280 104v42M268 146h24M268 157h24M280 157v70M390 104v42M378 146h24M378 157h24M390 157v70M500 104v42M488 146h24M488 157h24M500 157v70"/></g><text x="335" y="51" fill="#fbbf24" font-size="10" text-anchor="middle">series inductance L′·dx</text><text x="335" y="190" fill="#c4b5fd" font-size="10" text-anchor="middle">shunt capacitance C′·dx</text><rect x="621" y="58" width="70" height="207" fill="#3a1c1c" stroke="#f87171" stroke-width="2"/><path d="M642 84l27 25-27 25 27 25-27 25 27 25-27 25" fill="none" stroke="#fca5a5" stroke-width="3"/><text x="656" y="286" fill="#fca5a5" font-size="9.5" text-anchor="middle">ZL ≠ Z₀</text><path d="M100 78H605" stroke="#34d399" stroke-width="3" marker-end="url(#green)"/><text x="353" y="67" fill="#6ee7b7" font-size="10" text-anchor="middle">incident wave · velocity v = 1/√(L′C′)</text><path d="M605 245H121" stroke="#f87171" stroke-width="3" marker-end="url(#arrow)"/><text x="363" y="263" fill="#fca5a5" font-size="10" text-anchor="middle">reflected wave · ΓL = (ZL − Z₀)/(ZL + Z₀)</text></g><g transform="translate(87 371)"><path d="M0 42V0M0 42H586" stroke="#3a4453"/><path d="M8 38h93V13h190v13h194v6h93" fill="none" stroke="#60a5fa" stroke-width="2.5"/><g stroke="#64748b" stroke-dasharray="4 3"><path d="M101 0v42M291 0v42M485 0v42"/></g><g fill="#8b98a5" font-size="9" text-anchor="middle"><text x="101" y="60">one-way delay td</text><text x="291" y="60">reflection returns</text><text x="485" y="60">next round trip</text></g></g><text x="380" y="452" fill="#6b7684" font-size="11.5" text-anchor="middle">A wire becomes a transmission line when flight time is not negligible relative to edge rate; then termination controls signal integrity.</text></svg>

Verification, qualification, and CFS connection. Coupons and production traces are measured with TDR for impedance and delay and with a VNA for insertion loss, return loss, phase, and crosstalk. Deembedding moves the reference plane beyond fixtures and launches. Simulation-to-measurement correlation checks actual cross-section, copper profile, resin content, roughness, and material lot. Time-domain eyes and BER show system consequence. Temperature and humidity can alter material behavior. Acceptance limits distinguish local impedance excursions from length-weighted channel loss rather than compressing every property into one nominal Z0 number. Verification crosses schematic, layout, fabrication, assembly, and laboratory evidence. Automated checks cover connectivity, spacing, drill aspect ratio, annular ring, solder-mask dams, acid traps, copper balance, test access, and assembly courtyard. Field solvers and extracted models check impedance, loss, coupling, return paths, and PDN behavior. Fabrication coupons measure impedance; TDR locates discontinuities; VNA measurements characterize insertion and return loss; oscilloscopes measure eye, jitter, and rail noise. Thermal imaging, current injection, chamber cycling, vibration, X-ray, cross-section, and functional test close physical reliability. A design review preserves raw models, stackups, material declarations, process limits, measurement reference planes, calibration, uncertainty, failure evidence, and revision history so a passing prototype can become a repeatable product. Acceptance criteria distinguish nominal performance from guardband, screening, qualification, and production-control limits. Supplier substitutions trigger review of electrical, thermal, mechanical, chemical, assembly, and reliability assumptions rather than a part-number-only approval. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.