Trench Capacitor eDRAM Process is a specialized memory cell fabrication technology embedding dense capacitor structures within deep silicon trenches, achieving ultra-high capacitance density — enabling high-speed embedded DRAM for processor cache competing with traditional SRAM.

Trench Capacitor Architecture

EDRAM (embedded DRAM) integrates memory directly on logic die through vertical trench capacitors: deep narrow trenches (depth 5-20 μm, width 0.1-0.3 μm) etched into silicon, filled with conductor (polysilicon, metal) serving as capacitor bottom plate; silicon sidewalls form capacitor plates through junction formation (doping sidewalls to opposite conductivity). Oxide or ONO (oxide-nitride-oxide) dielectric separates plates achieving capacitance: C = ε₀×εᵣ×A/d, where A ∝ depth×width and d = dielectric thickness. Large aspect ratio (depth/width >100:1) provides area compression enabling capacitance without excessive footprint. Cell storage ~100-200 fF per trench — sufficient for 1-2 cells per SRAM footprint with comparable storage.

Trench Formation and Deep Etch

• Photolithography: Mask pattern defines trench locations; lithography resolution typically 0.5-1 μm despite narrow final width (0.1 μm) through RIE anisotropic etch
• Deep Reactive Ion Etching (DRIE): Bosch process (cycles of fluorine-based etch and polymer deposition) creates near-vertical 5-20 μm deep trenches; polymer deposition prevents lateral etch (passivation) enabling vertical walls
• Etch Selectivity: Fluorine plasma (SF₆, CF₄) selectively etches silicon; selectivity to SiO₂ >50:1 enabling controlled etch depth termination at underlying oxide
• Aspect Ratio Limits: Practical DRIE achieves 20:1 aspect ratio; extreme depths (>15 μm) with narrow widths require multiple etch/deposition cycles, increasing complexity

Trench Capacitor Dielectric

• ONO Stack: Thermal oxide (2-3 nm), silicon nitride (5-10 nm), thin oxide (1-2 nm) provides high capacitance: capacitance density ~1 μF/cm² versus single oxide ~0.2 μF/cm²
• High-κ Dielectrics: Hafnium oxide (HfO₂, κ ~25 versus SiO₂ κ=3.9) enables equivalent capacitance with thicker dielectric, improving yield/reliability through reduced defect density
• Formation: ONO deposited via thermal oxidation, CVD nitride deposition, oxidation, and annealing; high-κ materials deposited via ALD providing thickness control
• Capacitance Tunability: Higher capacitance density enables scaling — same stored charge with smaller cell area or deeper trench; practical limits: extremely thin dielectric increases leakage current, while thick dielectric reduces capacitance benefit

Buried Strap and Trench Access

Traditional DRAM bit-cell isolation (1T1C, one transistor connecting cell) incompatible with deep trench geometry. Buried strap technology creates electrical connection from trench bottom through silicon to surface-level transistor. Strap formation: polysilicon or metal via within trench structure connects internal storage capacitor to access transistor. Alternative: tungsten plug fills trench, contacts transistor at surface level. Strap resistance critical parameter — low resistance (~10-100 kΩ) enables fast charge transfer during read/write operations; high resistance creates RC time constant degrading refresh cycle speed.

Cell Organization and Peripheral Circuits

• Array Structure: Trenches organized in 2D array; typical 1T1C architecture with transistor at surface level, capacitor buried below
• Access Transistor: Conventional MOSFET selects cell; gate electrode controls charge transfer between bitline and capacitor
• Wordline/Bitline: Wordlines activate transistor gates row-by-row; bitlines carry cell charge during read operation
• Sense Amplifiers: Bitline charge (tens-of-picocoulomb) detected through differential sense amp; amplified voltage buffered for output

Refresh and Leakage Management

EDRAM cells retain stored charge through capacitance; however, junction leakage (diode reverse bias current) discharges capacitor requiring periodic refresh. Refresh frequency typically 1-2 MHz (refresh period 0.5-1 μs) higher than traditional DRAM due to reduced capacitance. Leakage current inverse exponentially temperature-dependent; elevated temperature operation (>80°C) increases refresh rate proportionally. Peripheral circuits include refresh controller managing automatic refresh cycles.

eDRAM vs SRAM Trade-offs

eDRAM provides 4-6x higher density than SRAM at comparable speed; drawback: requires refresh power and introduces refresh latency. Cache designs exploit eDRAM: backing large L4 cache with eDRAM enables 100+ MB cache capacity at 2-3x larger area versus L3 SRAM, improving application performance for memory-intensive workloads. Cost-per-bit dramatic: eDRAM 1-2¢/MB versus SRAM 5-10¢/MB at equivalent speed.

Closing Summary

Trench capacitor eDRAM represents a high-density alternative to SRAM-based cache through vertical capacitance exploitation in deep silicon trenches, combining semiconductor physics with advanced dielectric engineering to achieve unprecedented storage density — enabling energy-efficient processor cache scaling for data-center and scientific computing.