Embedded DRAM needed a way to pack a working capacitor into a logic-compatible process without stealing the planar area a stacked-capacitor DRAM cell would need, and the deep trench capacitor answered that by turning the storage node sideways, etching straight down into the silicon substrate instead of building up over it. A trench with an aspect ratio well above 50x turns a modest surface footprint into a large sidewall area, and it is that sidewall area, not the small top-down opening, that ultimately sets how much charge the cell can actually store. That single geometric decision, borrow depth instead of area, is what let eDRAM keep scaling storage density alongside the logic transistors sharing the same die, long after a planar stacked-capacitor approach would have run out of room in a logic-optimized layout.

Trench etch is the foundational step of the entire module, since every downstream layer, buried plate, dielectric, poly fill, and buried strap, has to conform to whatever profile the etch delivers deep into the substrate. A production deep trench commonly reaches 6 µm to 8 µm into the silicon at a top-opening critical dimension in the 100 nm to 150 nm range, giving an aspect ratio well above 50x that pushes the limits of what a single-step plasma etch can hold uniform from top to bottom. Sidewall angle through that depth is held close to vertical, typically within a couple ° of 90°, since even a slight taper compounds over several µm of depth into a meaningfully smaller capacitor area near the trench bottom than at the top. Etch uniformity across a wafer is commonly specified within a few % of target depth, since a trench that etches shallow in one region of the wafer directly produces a lower-capacitance, weaker-retention cell in that region. Bottom CD is typically held to within about 15% of the top-opening CD across the full 6 µm to 8 µm depth, a bow-and-taper tolerance that keeps sidewall area, and therefore capacitance, predictable trench to trench across a dense array.

The buried plate forms one electrode of the capacitor and is created by diffusing dopant outward from the trench sidewall into the surrounding silicon, effectively turning a ring of substrate around each trench into a shared, continuously connected electrode. This diffusion step is typically driven at an elevated temperature for a duration tuned to reach a target plate depth without excessively widening the diffusion profile into neighboring trenches, since trench-to-trench spacing at advanced density has shrunk to the point where lateral diffusion overlap is a real design constraint. Plate dopant concentration is chosen to keep buried-plate sheet resistance low enough that it does not become a bottleneck when many trenches switch simultaneously across a dense array. A buried plate resistance target of a few ohm per square is common, since a higher value can measurably slow access to trenches far from the plate's contact point in a large array. Plate diffusion is typically driven at a temperature in the 900 °C to 1000 °C range, and the resulting plate depth commonly extends 0.1 µm to 0.3 µm laterally from the trench sidewall into the surrounding silicon.

The capacitor dielectric, whether a classic ONO stack of oxide-nitride-oxide or a high-k alternative, is grown or deposited as an extremely thin film that has to coat the entire trench sidewall conformally from the top opening down to the trench bottom. An ONO dielectric equivalent oxide thickness commonly falls in the 4 nm to 6 nm range, thin enough to deliver high capacitance per unit area while still holding leakage current low enough for multi-second retention. High-k dielectric alternatives can reach a meaningfully higher capacitance per unit area at a comparable or even larger physical thickness, since the higher dielectric constant relative to silicon oxide directly boosts capacitance without requiring the film to be made thinner and consequently leakier. Interface quality between the dielectric and the surrounding silicon is checked closely, since trap density at that interface directly determines how quickly stored charge leaks away and therefore how often the cell must be refreshed to hold valid data. Dielectric thickness uniformity from trench top to trench bottom is commonly held within about 10% of target, since a thin spot anywhere along that sidewall becomes the leakage-limiting point for the entire cell.

Polysilicon fill completes the trench capacitor's second electrode, and filling a sub-150 nm opening to a depth of several µm without leaving a void or seam is a nontrivial deposition challenge in its own right. Fill poly is typically doped in situ during deposition to keep resistivity low without a separate implant step that a deep, narrow trench geometry would make difficult to execute uniformly. A collar oxide is commonly formed near the top of the trench before poly fill to isolate the upper poly region from the substrate, preventing a parasitic leakage path that would otherwise appear near the trench's shallow end where the buried plate is not present. Void-free fill is verified across a representative sample using cross-section inspection, since an internal seam or void in the poly fill can silently reduce effective capacitor area without producing an obvious surface-level defect.

The buried strap is the connection that makes the whole structure useful: a conductive path linking the trench's poly fill directly to the source-drain region of the access transistor sitting at the surface, formed by controlled dopant outdiffusion from the poly into the adjacent silicon. Because the buried strap sits at a specific depth below the surface, its formation has to be tightly controlled so it reliably contacts the access transistor's junction without diffusing so far that it shorts to the buried plate below or drifts into a neighboring structure. Strap resistance is kept low, commonly targeted below a few hundred ohm per contact, since a high-resistance strap slows the read and write access time for that particular storage cell relative to the rest of the array. Strap formation is generally driven at a temperature near 850 °C to 950 °C for a duration on the order of tens of s, short enough to limit lateral diffusion spread to well under 0.1 µm beyond the intended contact region. Strap formation temperature and duration are qualified as tightly as any other thermal step in the flow, since this is one of the few places in a trench-capacitor process where a purely geometric misalignment, not just a film-property drift, can produce a fully non-functional cell.

Capacitance per cell, leakage, and data retention time are the three numbers that ultimately define whether the trench capacitor module meets its eDRAM specification, and all three trace back to the same sidewall area, dielectric thickness, and buried-plate quality already discussed. A typical target cell capacitance falls in the 20 fF to 40 fF range, a value chosen to hold enough charge that a sense amplifier can reliably distinguish a stored one from a stored zero after whatever leakage occurs between refresh cycles. Leakage current per cell is held low enough to support a refresh interval compatible with the eDRAM's target application, and a dielectric or junction leakage increase of even a few tens of % over the qualified specification can shrink the usable refresh window enough to fail a system-level retention test. Retention margin is typically qualified with several % of design guardband beyond the minimum system requirement, since process variation across a large array means the weakest cell, not the average cell, sets the real retention limit. Sense-amplifier margin is generally validated against a worst-case cell capacitance several % below the array mean, and a refresh interval is chosen so that even that weakest cell retains a readable signal across the full interval between refresh cycles.

Etch deep trench 6-8 um into substrate → Diffuse buried plate electrode from trench sidewall → Deposit thin ONO or high-k capacitor dielectric → Form collar oxide near trench top → Deposit doped poly fill electrode → Form buried strap to access transistor S/D → Verify capacitance, leakage, and retention margin

Viewed through a deep-trench capacitance engineering lens, the entire module is an exercise in turning a narrow, deep hole in silicon into a reliable, leakage-controlled charge-storage element, where etch depth and aspect ratio, dielectric thickness, buried-plate quality, and buried-strap integrity all have to land within tight margins simultaneously for the finished eDRAM cell to hold its data through every refresh interval it is asked to survive.