A trench power MOSFET is a vertical switch with a gate along etched p-body sidewalls. Above threshold, channels connect top sources to the drift region and backside drain. Dense cells reduce channel resistance but increase gate area, coupling, corner field, and process sensitivity.

Read trench power MOSFETs through a specific-on-resistance/voltage trade-off lens rather than a plain-switch lens. The drift layer must block rated voltage, yet its thickness and low doping raise resistance. Trench cells reduce channel and constriction terms, while superjunction pillars reshape depletion so n regions can be more heavily doped. Gate area and overlap determine switching loss. The useful figure of merit joins RDS(on), gate charge, breakdown voltage, temperature, and operating conditions.

The drift region pays for blocking voltage. In the off state, the p-body/n-drift junction depletes into the lightly doped epi and supports the drain field. A low-voltage example might use a 6 µm drift layer for a 60 V class device, while a higher-voltage silicon design may require tens of µm. Increasing drift doping reduces resistance but raises peak field and lowers avalanche margin. Breakdown must be measured as a distribution with defined leakage, temperature, ramp rate, and termination structure, because the cell core is not the only high-field region.

Edge termination spreads field at the active boundary. A 600 V cell may withstand 650 V in its core yet fail near 500 V with a poor edge. Termination dose and oxide need dedicated monitors; neither a core-only test nor a strong edge proves the whole die.

The trench converts density into oxide-field risk. A representative trench may be 2 µm deep with a 1 µm opening and 40 nm gate oxide, although voltage class and generation change all three. Sidewall angle sets channel geometry and poly fill; bottom curvature sets electric-field crowding; scallops and microtrenching create local oxide-thickness variation. A 5 nm oxide loss at one corner is proportionally large against a 40 nm target. AFM on representative etched surfaces and cross-sectional microscopy can distinguish roughness, bow, footing, and corner radius before oxidation hides the silicon surface.

Gate oxidation must passivate damaged sidewalls. ellipsometry monitors planar witnesses but not buried corners, so capacitors and cross-sections anchor the trench relationship. XPS can evaluate pre-oxidation residue. Voltage stress and breakdown distributions test whether nominal thickness behaves as a dielectric.

The p-body and source implants place the channel and parasitic diode. Body depth, dose, and lateral diffusion set channel length, threshold, punch-through margin, and the body-diode junction. The n+ source must overlap the channel without shorting or consuming the p+ body contact. SIMS can profile body and source dopants on suitable structures, but curvature and lateral gradients require cross-sectional or calibrated process simulation support. A 100 nm junction shift can change channel resistance and threshold even if top-down implant dose monitors remain centered.

Source metal shorts n+ source to p+ body to suppress the parasitic NPN. Contact depth must reach the body without cutting through its junction. Resistance raises heating; incomplete contact raises avalanche risk. Kelvin structures separate contact and sheet terms, while four-point probe maps suitable monitor films.

On-resistance is a sum of temperature-dependent components. The measured value contains source/contact, channel, accumulation, spreading, drift, substrate, and backside-metal contributions. At low voltage, channel and contact terms can dominate; at higher silicon voltage, drift resistance becomes decisive. An illustrative device measuring 0.010 ohm at 25°C may reach 0.018 ohm at 150°C. At 100 A, the 25°C value implies 100 W instantaneous conduction loss; at 50% duty before thermal feedback, that contribution averages 50 W.

That arithmetic is not a thermal solution. Junction temperature depends on transient impedance, attach, package, cooling, and pulse duration. A 100 µs pulse can pass where 10 s operation overheats. Measure RDS(on) across gate bias and temperature using pulses when self-heating matters. NIST-traceable references support—but do not define—the limit.

Switching loss exposes the gate-area penalty of dense cells. The driver must move charge associated with gate-source and gate-drain capacitances; the drain-voltage transition is strongly coupled to the Miller region. Narrower pitch can reduce channel resistance while increasing total gate area and charge. Split-gate or shielded-gate trenches can reduce gate-drain coupling, but introduce added oxide interfaces, field plates, and alignment demands. RDS(on) multiplied by gate charge is useful for comparing related devices only when voltage class, die area, gate drive, and measurement method are comparable.

An illustrative hard-switching estimate makes the operating-point dependence visible. With 400 V, 20 A, 20 ns voltage-current overlap on both turn-on and turn-off, and 100 kHz operation, the idealized overlap term is about 16 W. Changing edge time to 40 ns doubles that term before diode, capacitance, ringing, or gate-drive losses are included. Faster switching can reduce overlap but raise overshoot and electromagnetic stress through package and loop inductance. The optimum gate resistance belongs to the circuit, not only the die.

The body diode is part of the power stage. Reverse conduction uses the p-body/n-drift junction unless synchronous gate drive creates a channel path. Stored charge and reverse recovery can generate current spikes and loss when commutated. Lifetime control may improve recovery but increase forward drop or leakage, and superjunction structures have their own depletion and capacitance behavior. Test conditions must state forward current, di/dt, reverse voltage, temperature, and gate bias; one reverse-recovery number is not portable across circuits.

Keysight analyzers can acquire output, transfer, capacitance, breakdown, and pulsed characteristics; Keithley equipment supports leakage and threshold structures. Gate-charge tests must declare drain current, voltage, drive, and fixture. Report voltage-dependent capacitance as curves. Double-pulse testing adds switching, overshoot, ringing, and diode interaction.

Superjunction performance depends on charge balance, not pillar appearance. Alternating p and n pillars deplete laterally in the off state, allowing the n pillars to carry higher doping than a conventional drift region at similar voltage. The ideal benefit requires the integrated p and n charges to match across depth and wafer. A 5% dose, width, or taper imbalance can shift breakdown and capacitance behavior. Published analyses show that sensitivity to imbalance is strongest near designs optimized for minimum specific resistance, so production designs may intentionally sacrifice some resistance for process margin.

Superjunction fabrication may use repeated epitaxy and implantation, deep-trench fill, or other pillar-forming sequences. Repeated epi/implant offers profile segmentation but accumulates overlay and dose error. Deep-trench filling reduces some repetition while adding high-aspect-ratio etch, sidewall taper, void, and refill-uniformity risks. A 40 µm pillar with a 4 µm pitch has a 10 × depth-to-pitch ratio; small taper changes its integrated charge. SIMS, spreading-resistance or electrical profiling, cross-section, and breakdown mapping must be correlated rather than relying on nominal mask width.

Dynamic RDS(on) and output capacitance expose effects static tests miss. Traps can change resistance after 400 V off-state stress, while pillar depletion makes capacitance strongly voltage-dependent. Report stress voltage, dwell, delay, current, temperature, and repetition. DLTS identifies deep levels, but pulsed device tests reproduce the field history.

Backside processing closes the current path. Thinning reduces substrate resistance and thermal length but adds stress and damage. An illustrative wafer may move from 725 µm to 150 µm before backside preparation and metal; 100 µm can reduce resistance further while increasing handling risk. Adhesion, voiding, and die attach require qualification.

Set voltage, current, switching, avalanche, and thermal requirements
  -> Grow and map n-drift epitaxy or superjunction starting structure
  -> Etch trenches with depth, taper, corner, and damage controls
  -> Clean sidewalls and grow qualified gate oxide
  -> Fill poly-Si gate and clear overburden without trench voids
  -> Implant and activate p-body, n+ source, and p+ body contact
  -> Form aligned source/body contacts, passivation, and top metal
  -> Build termination and field-plate structures around active cells
  -> Thin backside, prepare drain contact, and deposit backside metal
  -> Map oxide integrity, dopant profiles, sheet and contact resistance
  -> Measure threshold, leakage, BV, RDS(on), capacitance, and gate charge
  -> Run double-pulse, diode recovery, avalanche, short-circuit, and aging tests
  -> Correlate failures to trench, oxide, body, drift, pillars, edge, and package
  -> Release only when static, dynamic, and thermal distributions overlap

Production release requires a coupled loss-and-field argument. The vertical channel, drift layer, superjunction balance where used, gate oxide, body contact, edge termination, backside path, and package must all support the intended waveform. A low room-temperature RDS(on) does not compensate for weak oxide corners, excessive gate charge, dynamic resistance, poor diode recovery, or insufficient breakdown margin. That specific-on-resistance/voltage trade-off lens keeps cell density tied to the blocking, switching, and reliability evidence that makes a power MOSFET usable.