Trigger voltage is the voltage threshold at which an ESD protection clamp activates and begins conducting current to protect sensitive internal circuits — representing the critical boundary between the clamp's off-state during normal operation and its on-state during an electrostatic discharge event.

What Is Trigger Voltage?

• Definition: The voltage (Vt1) at which an ESD protection device transitions from a high-impedance off-state to a low-impedance conducting state, initiating the discharge of ESD current.
• Avalanche Breakdown: In MOSFET-based clamps (GGNMOS), the trigger voltage corresponds to the drain-source avalanche breakdown voltage where impact ionization generates enough substrate current to turn on the parasitic bipolar transistor.
• RC Detection: In RC-triggered power clamps, the trigger voltage is determined by the RC network that detects fast voltage transients characteristic of ESD events.
• Diode Turn-On: In diode-based clamps, triggering occurs at the forward bias voltage (typically 0.7V per diode).

Why Trigger Voltage Matters

• Too High: If the trigger voltage exceeds the protected device's oxide breakdown voltage, the internal circuit is damaged before the clamp activates — the protection fails completely.
• Too Low: If the trigger voltage is too close to VDD, normal power supply noise, fast clock edges, or power-on ramps can falsely trigger the clamp, causing functional failures or excessive leakage.
• ESD Window Compliance: The trigger voltage defines the upper boundary of the clamp's operating regime and must fit within the ESD design window (Vh < Vt1 < BV_oxide).
• CDM Requirements: CDM events have sub-nanosecond rise times — the trigger mechanism must respond faster than the voltage ramp at the protected node.
• Temperature Dependence: Avalanche breakdown voltage typically has a positive temperature coefficient, meaning Vt1 increases at high temperature — designs must account for worst-case corner conditions.

Trigger Voltage by Clamp Type

Design Techniques for Trigger Voltage Control

• Channel Length Adjustment: Longer GGNMOS channels increase Vt1 by raising the breakdown voltage — shorter channels lower it.
• Implant Engineering: Additional implants (LDD, halo) can tune the drain junction breakdown voltage and therefore Vt1.
• Trigger Assist Circuits: External trigger circuits (diode chains, GGNMOS trigger taps) can actively lower the effective Vt1 of SCR-based clamps.
• Stacking: Cascode or stacked device configurations increase the effective trigger voltage for high-voltage I/O applications.
• Silicide Blocking: Non-silicided drain regions increase ballast resistance and modify the I-V curve near the trigger point.

Measurement

• TLP Testing: Transmission Line Pulse applies fast rectangular pulses of increasing voltage to measure the exact I-V curve and identify Vt1 with nanosecond resolution.
• VF-TLP: Very Fast TLP (sub-nanosecond rise time) measures trigger behavior relevant to CDM events.
• TCAD Correlation: Sentaurus TCAD simulations predict Vt1 for new device structures before fabrication.

Trigger voltage is the most critical single parameter in ESD clamp design — set it too high and the chip dies before the clamp fires, set it too low and normal operation triggers the protection, making precise trigger voltage engineering essential for every ESD device.