TSMC process. refers to the logic, specialty, memory-adjacent, packaging, and design-enablement platforms offered by Taiwan Semiconductor Manufacturing Company. In leading logic, the widely recognized sequence moved from N7 to N5 and N3 FinFET families and then to N2 nanosheet gate-all-around, with A14 identified as a later platform. Each name covers variants tuned for performance, density, power, automotive, or extended lifecycle; it is not a literal physical gate length. Semiconductor economics couple very large fixed commitments to uncertain product demand. Architecture, software, verification, masks, process qualification, factories, equipment, substrates, packaging capacity, test time, and inventory must be funded before lifetime volume is known. At the leading edge, design and mask nonrecurring expense can reach hundreds of millions of dollars, while a greenfield logic fab can require well above ten billion dollars and years to ramp. Mature nodes remain economically important because analog, RF, power, embedded memory, display, sensor, connectivity, and control functions do not automatically benefit from maximum transistor density. Revenue therefore depends on product mix, wafer starts, die area, yield, package complexity, utilization, pricing, customer concentration, and the timing of replacement cycles—not merely nominal node.

Business model, market position, and economics. TSMC is a pure-play foundry: customers such as Apple, NVIDIA, AMD, Qualcomm, MediaTek, Broadcom, and many others own products while TSMC supplies qualified manufacturing and packaging services. Scale supports large process-development budgets, extensive IP and EDA enablement, multiple fabs, yield learning, and capacity. Customer concentration and geographic concentration remain strategic considerations, while new regional fabs require trained ecosystems and may have different cost structures and initial product mixes. Competitive advantage accumulates across reusable IP, talent, design methodology, process recipes, yield history, packaging know-how, developer tools, customer relationships, standards, and installed software. These assets reinforce one another but also create switching costs and concentration risk. A strong product can still lose if its toolchain is difficult, supply is constrained, total system cost is poor, or customers cannot qualify it in time. Conversely, an older node or architecture can remain attractive when it is stable, available, inexpensive, security-qualified, and supported for a decade. Roadmaps should be read as directional commitments; production readiness requires design kits, working silicon, repeatable yield, capacity, packaging, and customer shipments.

Technology, product architecture, and implementation. TSMC states that N7 entered volume production in 2018, N5 in 2020, and N3 in 2022. N7+ introduced EUV into foundry volume production. N2 changes transistor architecture to nanosheets, affecting device electrostatics, libraries, SRAM, analog behavior, design rules, and process integration. A14 is positioned as a further generation; current TSMC material targets volume production in 2028 rather than 2027. Packaging families such as CoWoS, InFO, and SoIC are critical for AI and chiplet systems and must scale alongside wafer technology. A credible comparison starts at the workload and system boundary. Peak arithmetic, core count, transistor count, or process label alone says little about useful performance. Engineers examine sustained throughput, tail latency, memory capacity and bandwidth, cache behavior, interconnect topology, I/O, precision support, compiler maturity, power envelopes, cooling, reliability, security, serviceability, and software portability. For process and manufacturing choices they add density by circuit type, voltage range, SRAM scaling, analog behavior, design rules, IP readiness, yield learning, reticle limits, packaging, and qualification. Published specifications are usually conditional on product configuration and workload, so normalized measurements and clear test conditions matter.

Execution, supply chain, and engineering risk. Marketing-node comparisons across foundries are unreliable without circuit data. Density varies between logic, SRAM, analog, and I/O; performance and power improvements depend on voltage, library, design, routing, workload, and variant. A process can be in volume production while allocation is tight or a specific package and IP combination is immature. Designers must account for reticle size, mask cost, EUV layers, defect density, die size, redundancy, package yield, thermal limits, and test. The operating system behind a shipped chip spans architecture, RTL, verification, physical design, signoff, tapeout, mask preparation, wafer fabrication, probe, assembly, final test, firmware, drivers, libraries, system validation, and field support. A schedule slip in one layer can idle investment elsewhere. Capacity reservations, long-lead equipment, substrate allocation, export controls, geographic concentration, single-source materials, and qualified second sources shape resilience. Quality systems must connect inline process data to wafer sort, package test, board behavior, and field returns. Change control is especially strict for automotive, industrial, medical, aerospace, infrastructure, and other products with long service lives.

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  <text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">TSMC — Process Node Roadmap and Fab Network</text>
  <text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">the world's leading-edge foundry: 60%+ logic market share, sole supplier of most AI chips</text>

  <!-- === PROCESS NODE ROADMAP (left, descending) === -->
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  <text x="225" y="80" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">Process Node Roadmap</text>

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  <!-- N7 -->
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  <text x="157" y="105" fill="#8b98a5" font-size="9" text-anchor="middle">N7 (2018) — FinFET, DUV</text>
  <text x="260" y="105" fill="#6b7684" font-size="8">Apple A12, AMD Zen 2</text>

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  <text x="157" y="145" fill="#93c5fd" font-size="9" text-anchor="middle">N5 (2020) — FinFET, EUV</text>
  <text x="260" y="145" fill="#8b98a5" font-size="8">A14, M1, Zen 4, A100</text>

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  <text x="157" y="180" fill="#93c5fd" font-size="9" text-anchor="middle">N4/N4P (2022) — FinFET</text>
  <text x="260" y="180" fill="#8b98a5" font-size="8">H100, A17, M3</text>

  <!-- N3 -->
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  <text x="157" y="215" fill="#c4b5fd" font-size="9" text-anchor="middle">N3/N3E (2023) — FinFET</text>
  <text x="260" y="215" fill="#8b98a5" font-size="8">A17 Pro, M3 Pro/Max</text>

  <!-- N2 -->
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  <text x="157" y="255" fill="#6ee7b7" font-size="9" text-anchor="middle" font-weight="600">N2 (2025) — GAA nanosheet</text>
  <text x="260" y="255" fill="#34d399" font-size="8">first GAA node</text>

  <!-- A16 -->
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  <text x="157" y="293" fill="#fbbf24" font-size="9" text-anchor="middle" font-weight="600">A16 (2026) — GAA + BSPDN</text>
  <text x="260" y="293" fill="#fbbf24" font-size="8">backside power delivery</text>

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  <text x="157" y="330" fill="#fca5a5" font-size="9" text-anchor="middle">A14 (2028) — next-gen</text>
  <text x="260" y="330" fill="#6b7684" font-size="8">high-NA EUV?</text>

  <!-- Node labels -->
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  <text x="395" y="145" fill="#6b7684" font-size="7.5">EUV single-pattern</text>
  <text x="395" y="215" fill="#6b7684" font-size="7.5">EUV double-pattern</text>
  <text x="395" y="255" fill="#6b7684" font-size="7.5">gate-all-around</text>
  <text x="395" y="293" fill="#6b7684" font-size="7.5">backside power</text>

  <!-- === RIGHT TOP: Fab network === -->
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  <text x="582" y="80" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">Fab Network (2025)</text>

  <text x="455" y="100" fill="#34d399" font-size="9.5" font-weight="600">Taiwan (HQ)</text>
  <text x="455" y="114" fill="#8b98a5" font-size="9">Fab 18 (N5/N3), Fab 20/22 (N2)</text>
  <text x="455" y="126" fill="#6b7684" font-size="8">Hsinchu, Tainan, Kaohsiung</text>

  <text x="455" y="146" fill="#60a5fa" font-size="9.5" font-weight="600">Arizona, USA</text>
  <text x="455" y="160" fill="#8b98a5" font-size="9">Fab 21 (N4/N3, 2025 ramp)</text>

  <text x="455" y="178" fill="#c4b5fd" font-size="9.5" font-weight="600">Japan (Kumamoto)</text>
  <text x="455" y="192" fill="#8b98a5" font-size="9">JASM: N12-N6 (2024 online)</text>

  <!-- === RIGHT BOTTOM: Key numbers === -->
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  <text x="582" y="223" fill="#e6edf3" font-size="11" text-anchor="middle" font-weight="600">By the Numbers</text>

  <text x="455" y="243" fill="#8b98a5" font-size="9.5">Revenue: ~90B USD (2024)</text>
  <text x="455" y="259" fill="#8b98a5" font-size="9.5">CapEx: ~30B USD/yr</text>
  <text x="455" y="275" fill="#8b98a5" font-size="9.5">Leading-edge share: >90% (sub-7nm)</text>
  <text x="455" y="291" fill="#8b98a5" font-size="9.5">Wafer starts: ~2M 12" eq/month</text>
  <text x="455" y="307" fill="#8b98a5" font-size="9.5">Employees: ~70,000</text>
  <text x="455" y="325" fill="#fbbf24" font-size="9.5">Top customers: Apple, NVIDIA, AMD,</text>
  <text x="455" y="339" fill="#fbbf24" font-size="9.5">Qualcomm, Broadcom, MediaTek</text>
  <text x="455" y="353" fill="#6b7684" font-size="8.5">ASML is sole EUV supplier to TSMC</text>

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  <text x="380" y="380" fill="#e6edf3" font-size="10" text-anchor="middle" font-weight="600">Geopolitics: TSMC makes ~90% of the world's most advanced chips — all in Taiwan, 100 miles from China</text>
  <text x="380" y="396" fill="#8b98a5" font-size="9.5" text-anchor="middle">US CHIPS Act, Japan JASM, EU Chips Act — all trying to reduce concentration risk through new fabs</text>
  <text x="380" y="410" fill="#6b7684" font-size="8.5" text-anchor="middle">But leading-edge fabs take 3-5 years + 20B+ USD each — TSMC's head start is measured in decades</text>

  <!-- Transistor density comparison -->
  <text x="380" y="435" fill="#e6edf3" font-size="9.5" text-anchor="middle" font-weight="600">Density: N7=91 MTr/mm² → N5=173 → N3=292 → N2=~400 → A16=~500+ MTr/mm²</text>

  <text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">TSMC is the factory of the digital world — if it stops, AI training stops, phone production stops, everything stops.</text>
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Evaluation, roadmap discipline, and CFS connection. A node decision should use representative block implementation, SRAM and analog qualification, PDK maturity, IP availability, foundry signoff, schedule, wafer and mask economics, yield assumptions, package capacity, and lifecycle. Roadmap dates are milestones, not guarantees for every customer product. Treat N2 and A14 characteristics as platform-specific and distinguish target, risk production, qualification, and customer volume. Due diligence separates measured facts from marketing categories and forward-looking plans. Check the date, product form factor, memory configuration, power limit, software release, process variant, package, and whether a number is peak, typical, estimated, or independently reproduced. Company revenue rankings and foundry shares move with cycles, currency, reporting boundaries, and whether wafer manufacturing or end-product sales are counted. Procurement adds total landed cost, supply assurance, licensing terms, support, lifecycle, compliance, and exit options. Engineering teams should preserve traceable assumptions and revisit them when a roadmap, regulation, yield curve, or workload changes. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.