A through-silicon via (TSV) is a vertical copper connection etched straight through a thinned silicon die, carrying signals and power between its front and back surfaces. TSVs are what make true 3D integration possible: instead of wiring chips only at their edges, you stack them and connect them face-to-back through the silicon itself — the enabling technology behind HBM and 3D-stacked logic.\n\nIt is a deep hole through silicon, lined and filled with copper. Fabrication drills a high-aspect-ratio via (roughly 5-10 µm wide but tens of microns deep), lines it with an oxide liner for electrical isolation, adds a barrier and seed layer, then electroplates it full of copper. The die is thinned from the back until the copper is revealed, so the via now connects top-side circuitry to backside contacts. Microbumps at those contacts then bond one die's TSVs to the die stacked beneath it.\n\nVertical beats perimeter — thousands of short links instead of a few long ones. Traditional 2D packaging wires chips only around their edges (wire bonding or edge routing), which limits both the number of connections and their length. TSVs run the connection through the die, so a stack can have thousands of parallel vertical paths, each only tens of microns long. Short and dense means high bandwidth at low energy per bit — exactly the recipe an HBM stack uses to feed an accelerator, and what 3D-stacked cache and logic exploit.\n\n| Step | Purpose |\n|---|---|\n| Deep via etch | drill high-aspect-ratio hole through silicon |\n| Oxide liner | electrically isolate copper from the silicon |\n| Barrier + seed | block copper diffusion, start plating |\n| Copper electroplate | fill the via void-free |\n| Backside reveal | thin the die until the TSV is exposed |\n\n``svg\n\n``\n\nThe hard parts are stress, voids, and thinning. Copper and silicon expand at different rates, so a filled TSV creates a stress field (a keep-out zone where nearby transistors shift) and can crack or delaminate over thermal cycles. Voids left during plating raise resistance and hurt reliability, and thinning a wafer to expose the vias makes it fragile to handle. TSV resistance, capacitance, induced stress, voiding, and cracking are all first-order reliability concerns — which is why so much of the process is about filling and revealing the via cleanly.\n\nRead the TSV through a quant lens rather than a plumbing lens: what matters is interconnect density (vias per mm²), the resistance and capacitance per via, and the energy-per-bit of a vertical hop versus an edge route. Per the roofline, HBM's bandwidth to the accelerator is built from thousands of these short parallel vias, so the design question is how many low-RC TSVs you can pack and reveal reliably — a measured density-and-parasitics budget, not just 'a hole through the chip.'