TSV Barrier and Seed is the dual-layer metallization deposited on TSV sidewalls after the dielectric liner to enable copper electroplating — consisting of a thin (10-30 nm) diffusion barrier layer (TaN, TiN, or Ta) that prevents copper atoms from migrating through the liner into silicon, and a copper seed layer (100-200 nm) that provides the conductive surface required for electrochemical copper deposition to fill the via.
What Is TSV Barrier and Seed?
- Definition: Two sequential thin-film depositions inside the lined TSV — first a refractory metal or metal nitride barrier that blocks copper diffusion, then a thin copper layer that serves as the cathode for subsequent electroplating, together enabling void-free copper fill while protecting the silicon substrate from copper contamination.
- Barrier Layer: TaN (tantalum nitride) or Ta (tantalum) deposited by PVD (sputtering) or ALD at 10-30 nm thickness — must be continuous and pinhole-free on all via surfaces because even a single nanometer-scale gap allows copper diffusion that can kill transistors within months.
- Seed Layer: Copper deposited by PVD sputtering at 100-200 nm thickness — must be continuous on sidewalls and bottom to provide a uniform current path for electroplating; discontinuous seed causes void formation during plating.
- Conformality Challenge: PVD is inherently directional (line-of-sight deposition), making it difficult to coat the bottom and lower sidewalls of high-aspect-ratio TSVs — ionized PVD (iPVD) and ALD address this by providing more conformal deposition.
Why Barrier and Seed Matter
- Copper Containment: Copper is a fast diffuser in silicon and SiO₂ — without a barrier, copper atoms migrate through the liner into the silicon substrate within hours at elevated temperatures, creating deep-level traps that increase leakage current and degrade transistor performance.
- Plating Enablement: Copper electroplating requires a continuous conductive surface (the seed) to carry the plating current — gaps in the seed layer create areas where no copper deposits, leading to voids that increase resistance or cause open circuits.
- Adhesion: The barrier layer provides adhesion between the dielectric liner and the copper fill — poor adhesion leads to delamination during thermal cycling, a critical reliability failure mode.
- Electromigration Resistance: The barrier/copper interface affects electromigration lifetime — a well-adhered barrier constrains copper grain boundary diffusion, extending the via's current-carrying lifetime.
Deposition Methods
- PVD (Sputtering): Standard method for both barrier and seed — fast and cost-effective but conformality degrades at aspect ratios > 5:1; bottom coverage can drop below 10% of top thickness.
- Ionized PVD (iPVD): Uses a secondary plasma to ionize sputtered atoms, which are then directed by substrate bias into the via — improves bottom coverage to 20-40% at aspect ratios up to 10:1.
- ALD Barrier: Atomic layer deposition of TaN or TiN provides near-perfect conformality (> 95%) at any aspect ratio — used for the barrier layer when PVD conformality is insufficient.
- CVD Seed: Chemical vapor deposition of copper from Cu(hfac) precursors provides better conformality than PVD — used for high-aspect-ratio TSVs where PVD seed is discontinuous.
- Electroless Cu Seed: Chemical (non-electrolytic) copper deposition provides conformal seed coverage without line-of-sight limitations — emerging alternative for ultra-high-aspect-ratio TSVs.
| Layer | Material | Thickness | Method | Conformality | Function |
|-------|---------|-----------|--------|-------------|----------|
| Barrier | TaN | 10-20 nm | PVD/ALD | 30-95% | Cu diffusion block |
| Barrier | Ta | 10-30 nm | PVD | 20-40% | Adhesion + barrier |
| Barrier | TiN | 5-15 nm | ALD | > 95% | Ultra-conformal barrier |
| Seed | Cu | 100-200 nm | PVD/iPVD | 10-40% | Plating cathode |
| Seed | Cu | 50-100 nm | CVD | 60-80% | High-AR seed |
| Seed | Cu | 20-50 nm | Electroless | > 80% | Conformal seed |
TSV barrier and seed layers are the critical metallization foundation for copper-filled through-silicon vias — providing the diffusion barrier that protects silicon from copper contamination and the conductive seed that enables void-free electroplating, with conformality in high-aspect-ratio geometries remaining the central process challenge driving innovation in deposition technology.