TSV Cracking is a mechanical failure mechanism where fractures develop in the dielectric liner, diffusion barrier, or surrounding silicon of a through-silicon via — typically initiating at stress concentration points created by Bosch process scallops on the via sidewall, propagating under thermal cycling stress, and ultimately causing copper diffusion into silicon (if the barrier cracks) or electrical shorts (if cracks connect adjacent structures).

What Is TSV Cracking?

• Definition: The formation and propagation of fractures in the thin-film layers (SiO₂ liner, TaN barrier) or bulk silicon surrounding a TSV, driven by thermo-mechanical stress from CTE mismatch between copper and silicon, concentrated at geometric discontinuities on the via sidewall.
• Scallop-Induced Cracking: The Bosch process creates periodic scallops (50-200 nm amplitude) on the TSV sidewall — these scallops act as stress concentration points where the local stress is 2-5× higher than the nominal stress, making them the primary crack initiation sites.
• Liner Cracking: The SiO₂ liner is brittle and cracks when tensile stress exceeds its fracture strength (~1 GPa) — cracks in the liner expose the barrier to direct contact with silicon and create paths for copper diffusion.
• Barrier Cracking: If the TaN/Ta barrier cracks after the liner fails, copper atoms diffuse directly into the silicon substrate — copper is a fast diffuser in silicon and creates deep-level traps that increase leakage current and degrade transistor performance within micrometers of the crack.

Why TSV Cracking Matters

• Copper Poisoning: A barrier crack allows copper to diffuse into silicon at rates of ~1 μm/hour at 200°C — copper contamination creates mid-gap traps that increase junction leakage by orders of magnitude, effectively killing transistors near the cracked TSV.
• Progressive Degradation: Cracks propagate under repeated thermal cycling — a TSV that passes initial qualification may develop cracks after thousands of thermal cycles in the field, causing latent reliability failures.
• Cascade Failure: A single cracked TSV can contaminate surrounding silicon, degrading multiple transistors and potentially causing die-level failure — the damage zone expands over time as copper continues to diffuse.
• Detection Difficulty: Liner and barrier cracks are nanometer-scale features buried inside high-aspect-ratio vias — they cannot be detected by standard electrical testing until copper diffusion has already caused measurable device degradation.

Cracking Prevention

• Scallop Reduction: Using shorter Bosch etch cycles (< 2 seconds) reduces scallop amplitude from 200 nm to < 50 nm, reducing stress concentration factors from 5× to < 2×.
• Scallop Smoothing: Post-etch isotropic silicon etch or thermal oxidation + oxide strip smooths scallops before liner deposition — reduces stress concentration at the cost of slightly enlarging the via diameter.
• ALD Liner/Barrier: Atomic layer deposition provides perfectly conformal coverage that follows scallop contours without thickness variation — eliminates the thin spots at scallop peaks that are vulnerable to cracking in PVD-deposited films.
• Compliant Liner: Polymer liners (BCB, polyimide) absorb stress through elastic deformation rather than cracking — providing a compliant buffer between the rigid copper and brittle oxide.
• Thermal Cycling Limits: Reducing the temperature excursion range (ΔT) and rate of temperature change reduces peak stress — design for operation within a narrower temperature range when possible.

TSV cracking is the insidious mechanical failure that bridges the gap between thermo-mechanical stress and electrical degradation — initiating at Bosch scallop stress concentrations and propagating through liner and barrier layers to enable copper contamination of silicon, requiring scallop minimization, conformal deposition, and compliant liner materials to ensure long-term TSV integrity in 3D integrated circuits.