TSV Formation is the multi-step fabrication process for creating through-silicon vias — vertical electrical connections that pass completely through a silicon wafer or die — involving deep reactive ion etching (DRIE) to create high-aspect-ratio holes, dielectric liner deposition for electrical isolation, barrier/seed layer deposition to prevent copper diffusion, and electrochemical copper plating to fill the vias, enabling the vertical interconnects that are fundamental to 3D integrated circuits and advanced packaging.

What Is TSV Formation?

• Definition: The complete process sequence for fabricating a through-silicon via from bare silicon to a fully functional vertical electrical conductor — encompassing via etching, insulation, metallization, and planarization steps that together create a low-resistance copper pathway through the silicon substrate.
• DRIE (Bosch Process): The standard etching technique — alternating cycles of SF₆ plasma etching (isotropic silicon removal) and C₄F₈ plasma passivation (sidewall polymer protection) create vertical holes with scalloped sidewalls, achieving aspect ratios of 5:1 to 20:1.
• Aspect Ratio: The ratio of via depth to diameter — typical production TSVs are 5-10 μm diameter × 50-100 μm deep (5:1 to 10:1 aspect ratio); higher aspect ratios enable smaller TSV footprint but are more difficult to etch and fill.
• Bottom-Up Fill: Copper electroplating must fill the via from bottom to top without creating voids — achieved using superfilling chemistry with accelerator, suppressor, and leveler additives that preferentially deposit copper at the via bottom.

Why TSV Formation Matters

• 3D Integration Backbone: TSVs are the vertical wiring that connects stacked dies in 3D ICs — without TSVs, there would be no HBM memory, no 3D NAND, no stacked image sensors, and no chiplet-based processors.
• Bandwidth Density: A single TSV carries one signal or power connection; thousands of TSVs in parallel provide the massive bandwidth (1-2 TB/s for HBM) that makes 3D stacking valuable for AI and high-performance computing.
• Electrical Performance: Copper-filled TSVs achieve < 50 mΩ resistance and < 50 fF capacitance per via — low enough for multi-GHz signaling between stacked dies with minimal power overhead.
• Thermal Conduction: Copper TSVs also serve as thermal conduits, helping extract heat from interior dies in multi-die stacks — critical for preventing thermal throttling in HBM and 3D logic.

TSV Formation Process Steps

• Step 1 — Via Etch (DRIE): Bosch process alternates SF₆ etch and C₄F₈ passivation cycles at 1-5 second intervals, creating vertical holes at 5-20 μm/min etch rate with < 0.5° sidewall taper. Equipment: Lam Research, SPTS, Oxford Instruments.
• Step 2 — Liner Deposition: 100-500 nm SiO₂ deposited by PECVD or thermal CVD to electrically isolate the copper conductor from the silicon substrate — must be conformal (uniform thickness on sidewalls and bottom).
• Step 3 — Barrier Layer: 10-30 nm TaN or TiN deposited by PVD or ALD to prevent copper atoms from diffusing through the oxide liner into the silicon — barrier integrity is critical for long-term reliability.
• Step 4 — Seed Layer: 100-200 nm copper deposited by PVD (sputtering) to provide the conductive surface needed for subsequent electroplating — must be continuous on sidewalls and bottom despite the high aspect ratio.
• Step 5 — Copper Electroplating: Bottom-up electrochemical deposition fills the via with copper over 30-120 minutes — superfilling additives create differential deposition rates that fill from the bottom up, preventing void formation.
• Step 6 — Anneal: 200-400°C anneal promotes copper grain growth and stress relaxation — large grains reduce resistivity and improve electromigration resistance.
• Step 7 — CMP: Chemical mechanical polishing removes excess copper (overburden) from the wafer surface, planarizing for subsequent processing.

TSV formation is the foundational fabrication process for 3D semiconductor integration — combining deep silicon etching, conformal dielectric and metal deposition, and void-free copper electroplating to create the vertical electrical highways that connect stacked dies, enabling the HBM memory, 3D processors, and advanced sensor architectures driving the future of semiconductor technology.