TSV Liner Deposition is the process of depositing a thin dielectric insulation layer on the sidewalls and bottom of an etched through-silicon via — typically 100-500 nm of SiO₂ deposited by PECVD or sub-conformal CVD, providing the electrical isolation between the copper conductor and the surrounding silicon substrate that prevents short circuits and copper contamination of active devices.

What Is TSV Liner Deposition?

• Definition: The deposition of a conformal dielectric film (SiO₂, Si₃N₄, or polymer) on all internal surfaces of the etched TSV hole to electrically isolate the metallic via conductor from the semiconducting silicon substrate — without this liner, the copper fill would directly contact silicon, creating a short circuit and contaminating nearby transistors.
• Conformality Challenge: The liner must uniformly coat the sidewalls and bottom of a high-aspect-ratio hole (5:1 to 10:1) — achieving uniform thickness from top to bottom is the primary process challenge, as deposition rate naturally decreases deeper in the via due to limited precursor transport.
• PECVD (Plasma-Enhanced CVD): The standard deposition method — TEOS (tetraethyl orthosilicate) + O₂ plasma at 200-400°C deposits SiO₂ with 50-80% step coverage in typical TSV geometries.
• Sub-Conformal CVD: For very high aspect ratios, thermal CVD or ALD (atomic layer deposition) provides better conformality (> 90% step coverage) but at lower deposition rates and higher cost.

Why TSV Liner Matters

• Electrical Isolation: The liner prevents direct electrical contact between the copper conductor and the silicon substrate — without it, the TSV would short to the substrate, and copper ions would diffuse into silicon, killing nearby transistors.
• Capacitance Control: The liner thickness and dielectric constant directly determine TSV capacitance (C_TSV ∝ ε/t_liner) — thicker liners reduce capacitance but consume more of the via diameter, increasing resistance.
• Reliability: Liner integrity must be maintained through all subsequent processing (barrier deposition, copper plating, annealing, CMP) and throughout the product lifetime — any crack or pinhole allows copper diffusion that causes progressive device degradation.
• Leakage Current: The liner must provide sufficient insulation to keep TSV-to-substrate leakage below specification (typically < 1 nA at operating voltage) — liner quality and thickness determine the leakage floor.

Liner Deposition Methods

• PECVD SiO₂ (TEOS): The production standard — 200-400°C deposition, 50-80% step coverage, 100-500 nm thickness. Fast (1-5 μm/min) but conformality degrades at high aspect ratios.
• Thermal CVD SiO₂: Higher conformality (70-90%) than PECVD but requires higher temperature (> 400°C) — used when PECVD conformality is insufficient.
• ALD SiO₂ or Al₂O₃: Near-perfect conformality (> 95%) at any aspect ratio — but extremely slow (0.1-1 nm/cycle, ~100 cycles/hour), making it cost-prohibitive for thick liners.
• Polymer Liner: Parylene or BCB deposited by vapor deposition — excellent conformality and low dielectric constant but limited thermal stability.
• Hybrid Approach: Thin ALD layer (10-20 nm) for pinhole-free coverage + thicker PECVD layer for bulk insulation — combines the conformality of ALD with the throughput of PECVD.

TSV liner deposition is the critical insulation step that enables copper-filled vias to coexist with silicon transistors — conformally coating high-aspect-ratio via sidewalls with dielectric material to provide the electrical isolation, capacitance control, and copper diffusion prevention essential for reliable through-silicon via interconnects in 3D integrated circuits.