TSV Reveal is the backside processing step that exposes the buried ends of through-silicon vias by thinning the wafer from the backside until the copper-filled vias protrude — grinding and etching the silicon substrate to a thickness slightly less than the TSV depth so that the copper "nails" extend beyond the silicon surface, enabling electrical connection to the next die or redistribution layer in a 3D stack.

What Is TSV Reveal?

• Definition: The process of thinning a wafer from the backside (by grinding, CMP, and/or wet/dry etching) to expose the bottom ends of TSVs that were fabricated from the front side — the TSVs, originally buried within the full-thickness wafer, become accessible for backside electrical connection.
• Protrusion: After silicon removal, the copper TSV tips protrude 1-5 μm above the silicon surface because the etch chemistry selectively removes silicon faster than copper — this protrusion is later planarized or used directly for bonding.
• Process Sequence: (1) Temporary bond device wafer face-down to carrier, (2) Backgrind from 775 μm to ~55 μm (TSVs are 50 μm deep), (3) CMP or wet etch to remove remaining 5 μm of silicon and reveal TSV tips, (4) Passivate exposed silicon backside.
• Selective Etch: The final reveal step uses a silicon etch that stops on the TSV liner (SiO₂) — typically SF₆-based dry etch or TMAH/KOH wet etch with high Si:SiO₂ selectivity (> 100:1).

Why TSV Reveal Matters

• Electrical Access: TSV reveal creates the backside access points needed to connect stacked dies — without reveal, the TSVs are buried and electrically inaccessible from the backside.
• Thickness Control: The final wafer thickness after reveal must be precisely controlled (±2 μm) — too thick and TSVs aren't exposed, too thin and the wafer is fragile and transistors may be damaged.
• Surface Quality: The revealed backside surface must be smooth and clean enough for subsequent processing — backside RDL, passivation, and micro-bump formation all require a well-prepared surface.
• Yield Critical: TSV reveal involves thinning a fully processed device wafer to < 50 μm while bonded to a carrier — any grinding damage, non-uniformity, or contamination at this stage destroys high-value devices.

TSV Reveal Process Steps

• Step 1 — Backgrinding: Mechanical grinding removes bulk silicon from 775 μm to ~55-60 μm — fast (5-10 min) but leaves subsurface damage (5-10 μm deep cracks and dislocations).
• Step 2 — Stress Relief: CMP or wet etch removes 5-10 μm of grinding-damaged silicon — eliminates subsurface cracks that would propagate during thermal cycling.
• Step 3 — Selective Si Etch: Dry etch (SF₆/O₂) or wet etch (TMAH) selectively removes silicon and stops on the TSV oxide liner — reveals the TSV tips protruding 1-5 μm above the silicon surface.
• Step 4 — Liner Recess: Optional etch to remove the oxide liner from the TSV tips, exposing bare copper for direct metal contact.
• Step 5 — Backside Passivation: Deposit SiO₂ or Si₃N₄ on the exposed silicon backside to prevent contamination and provide electrical isolation.
• Step 6 — Cu CMP: Planarize the protruding copper tips flush with the passivation surface if required for subsequent hybrid bonding.

TSV reveal is the precision backside thinning step that transforms buried vias into accessible interconnects — carefully removing silicon to expose copper TSV tips while maintaining thickness uniformity and surface quality, creating the backside electrical access points that enable die stacking and vertical signal routing in every 3D integrated circuit.