TSV Voiding is a reliability failure mechanism where voids (empty cavities) form within the copper fill of a through-silicon via — caused by incomplete electroplating during manufacturing, stress-driven vacancy migration during operation, or electromigration under high current density, resulting in increased electrical resistance, potential open circuits, and degraded thermal conductivity that can lead to 3D IC failure.

What Is TSV Voiding?

• Definition: The formation of gas-filled or vacuum cavities within the copper conductor of a TSV, reducing the effective cross-sectional area of the conductor and potentially creating complete electrical discontinuities (open circuits) if the void spans the full via cross-section.
• Plating Voids: Voids formed during copper electroplating when the bottom-up fill process fails — gas bubbles trapped at the via bottom, premature closure of the via mouth (pinch-off), or insufficient superfilling additive concentration create voids that are locked in during manufacturing.
• Stress Voids: Voids that nucleate and grow during thermal processing or operation due to tensile stress in the copper — vacancies migrate along grain boundaries toward stress concentration points, accumulating into voids over time.
• Electromigration Voids: Voids formed by current-driven copper atom transport — at high current densities (> 10⁵ A/cm²), copper atoms migrate in the direction of electron flow, depleting material at the cathode end and creating voids.

Why TSV Voiding Matters

• Resistance Increase: A void that occupies 10% of the via cross-section increases resistance by ~11% — for power delivery TSVs, this increases IR drop and can cause timing failures in the powered circuits.
• Open Circuit: A void spanning the full via cross-section creates a complete open circuit — catastrophic failure that renders the entire 3D stack non-functional if the affected TSV carries a critical signal or power connection.
• Thermal Degradation: Voids are thermal insulators — a voided TSV has reduced thermal conductivity, creating local hot spots in the 3D stack that can trigger thermal runaway or accelerate other failure mechanisms.
• Progressive Failure: Stress voids and EM voids grow over time — a TSV that passes initial testing may develop voids during field operation, causing latent failures that are difficult to screen.

Void Prevention and Detection

• Optimized Plating Chemistry: Superfilling additives (accelerators like SPS, suppressors like PEG, levelers like JGB) create differential deposition rates that fill from the bottom up — proper additive concentration and replenishment prevent pinch-off voids.
• Pre-Plating Anneal: Annealing the seed layer before plating improves grain structure and adhesion, reducing void nucleation sites.
• Post-Plating Anneal: 200-400°C anneal after plating promotes copper grain growth and stress relaxation, reducing the driving force for stress voiding.
• X-ray Inspection: Non-destructive X-ray microscopy or micro-CT can detect voids > 0.5 μm within TSVs — used for process development and sampling inspection.
• Electrical Testing: Resistance measurement of individual TSVs or daisy chains detects voids that increase resistance above specification — the primary production screening method.

TSV voiding is the primary electrical failure mechanism in copper-filled through-silicon vias — arising from manufacturing defects during electroplating or progressive vacancy accumulation during operation, requiring optimized plating chemistry, post-plating annealing, and rigorous inspection to ensure void-free TSVs that maintain their electrical and thermal performance throughout the product lifetime.