Tungsten Contact Plug Fill is a interconnect technology employing tungsten chemical vapor deposition to fill high-aspect-ratio contact vias with low resistance, followed by chemical-mechanical polishing — fundamental to interconnect hierarchy from transistor contacts through multilevel wiring.

Tungsten CVD Fundamentals

Tungsten chemical vapor deposition reduces tungsten hexafluoride (WF₆) with hydrogen at elevated temperature (200-400°C), depositing tungsten metal while gaseous HF byproduct exhausts:

WF₆ + 3H₂ → W + 6HF

Reaction temperature balances nucleation (low temperature favors) against deposition rate (high temperature favors). Industrial processes operate ~300-350°C; substrate temperature maintained via resistive heating maintaining ±10°C tolerance. Deposition rate highly temperature-dependent: ±1°C changes rate ~1-2%, requiring precise control for repeatable via fill thickness. Reactor pressure typically 5-10 Torr — lower pressure improves deposition uniformity (mean-free-path longer enabling conformal deposition on high-aspect-ratio features) but reduces deposition rate.

Nucleation and Conformal Deposition

• Nucleation Barrier: Tungsten CVD exhibits high nucleation barrier on oxide and dielectric surfaces; direct deposition on oxide surfaces occurs slowly unless seeded layer provided
• Seed Layer Approach: Tantalum or titanium nitride (1-5 nm) sputtered on contact surface provides nucleation site; nucleation proceeds rapidly on metal surface enabling conformal tungsten deposition
• Barrier Layer Integration: Tantalum or tungsten nitride barrier deposited via sputtering or ALD prevents tungsten diffusion into silicon or dielectric; thickness 5-50 nm depending on application
• Nucleation Chemistry: Tungsten nucleation assisted through fluorine species in precursor gas; fluorine enhances hydrogen reactivity and provides chemical pathway enabling nucleation on oxide surfaces

Via Fill and Thickness Control

Contact vias typically 100-500 nm diameter with aspect ratio (depth/diameter) 2-10:1. Tungsten CVD fills bottom-up: nucleation layer deposits first on via bottom; continued deposition builds conformal tungsten layer up sidewalls and eventually fills via completely. Critical parameter: stopping deposit before complete overfilling (creating topography), but ensuring sufficient fill preventing voids. Process monitoring: deposition time calibrated through test patterns with varying aspect ratios; deposition rate versus aspect ratio characterized enabling time prediction for target fill.

Tungsten Properties and Resistance

• Electrical Resistivity: Tungsten bulk resistivity 5.5 μΩ-cm; however, deposited CVD tungsten exhibits higher resistivity (8-15 μΩ-cm) due to grain boundaries, impurities, and defects trapping electron scattering
• Grain Structure: Tungsten CVD deposits as columnar grains (0.1-1 μm size); grain boundary scattering contributes ~30-50% of resistivity increase versus bulk
• Impurity Content: Hydrogen residue from CVD precursor incorporation in film creates defect states reducing mobility; fluorine residue similarly impacts conductivity
• Thermal Annealing: Post-deposition rapid thermal anneal (600-700°C, seconds) reduces defects and impurities improving resistivity by 10-20% but risks undesired diffusion into adjacent materials

Contact Etch Back Process

After tungsten CVD deposition and subsequent over-metal layer deposition, chemical-mechanical polishing (CMP) removes excess tungsten down to desired thickness. Etch-back alternative: selective tungsten etching through selective etchant removes tungsten above contact surface without attacking dielectric or oxide. Tungsten etch-back employs XeF₂ (xenon difluoride) gas-phase etchant at room temperature: WF₆ product forms volatile species enabling selective removal. Advantages: no mechanical contact (CMP) eliminating dishing/erosion damage, faster process, and simpler integration. Disadvantages: XeF₂ etch rate lower than CVD deposition rate requiring lengthy etch times; selectivity against dielectrics limited (gradual over-etch attacks underlying oxide).

Integration with Interconnect Stack

• Via-First Process: Tungsten plugs fill vias connecting active transistor region to first metal layer (metal-0 or M0); tungsten contact resistance (contact resistance + via resistance) critical for circuit delay and power
• Pitch and Scaling: Contact pitch reduction (45 nm, 36 nm nodes) requires smaller via diameter; aspect ratio increases stressing tungsten CVD conformal capability
• Multilevel Integration: Higher metal layers employ copper interconnect for superior conductivity; tungsten restricted to contacts/vias where conformal fill essential; copper ECP (electrochemical plating) suited for planar layer topology

Challenges and Process Optimization

Void formation common defect during tungsten CVD: incomplete fill or collapsed deposition on sidewalls creates trapped voids reducing electrical conductivity or causing open circuits. Prevention: optimized nucleation (sufficient seed layer), proper pressure/temperature to ensure conformal growth, and deposition time calibration. Seam formation (line defects along via center) occurs when sidewall deposition meets at top prematurely, trapping voids. Optimized deposition chemistry and pressure minimize seam formation risk.

Closing Summary

Tungsten CVD contact fill represents a critical interconnect technology leveraging thermally-driven reduction chemistry to achieve conformal filling of high-aspect-ratio features, maintaining low contact resistance while enabling planarization through etch-back — essential for scalable contact integration to advanced technology nodes.