Tunnel field-effect transistors replace thermionic emission with quantum-mechanical band-to-band tunneling as the carrier injection mechanism, offering a path to subthreshold swing below the 60 mV/decade thermal limit of conventional MOSFETs — but the physics that enables steep switching also constrains on-current, creates ambipolar leakage, demands heterojunction engineering, and tightens every interface and doping requirement beyond what planar CMOS integration has encountered.

The MOSFET subthreshold swing is thermally limited to $kT/q \cdot \ln(10) \approx 60$ mV/decade at room temperature because carrier injection relies on thermionic emission over a potential barrier. Reducing supply voltage below approximately 0.5 V while maintaining adequate on/off ratio requires a switching mechanism that filters the Boltzmann tail rather than riding it. Band-to-band tunneling (BTBT) achieves this by gating the alignment of valence and conduction bands across a thin, heavily doped junction: carriers tunnel quantum-mechanically through the forbidden gap rather than climbing over it, and the tunneling probability responds to gate voltage more steeply than thermal statistics allow.

The tunnel FET operates by modulating the width and height of the tunneling barrier with the gate electric field. In the off state, the source valence band and channel conduction band are misaligned, and the tunneling distance is large enough to suppress current exponentially. As the gate voltage increases, the bands bend until the source valence-band edge aligns with the channel conduction-band edge, opening a tunneling window. Current increases as the window widens and the tunneling distance shrinks. The subthreshold swing can be written $SS = (\partial \log_{10} I_D / \partial V_{GS})^{-1}$, and values below 60 mV/decade have been demonstrated in multiple material systems — though typically over only 1–3 decades of drain current, far less than the 4–6 decades available in MOSFETs.

Band-to-band tunneling probability depends exponentially on the tunneling distance and the effective bandgap. The WKB approximation gives the tunneling transmission as $T_{WKB} \approx \exp\left(-\frac{4\lambda\sqrt{2m^E_g^{3/2}}}{3q\hbar(\Delta\phi + E_g)}\right)$, where $\lambda$ is the screening tunneling length, $m^$ is the reduced effective mass, $E_g$ is the bandgap at the tunneling junction, $\Delta\phi$ is the energy window opened by the gate, and $\hbar$ is the reduced Planck constant. Smaller $E_g$, lighter $m^*$, and shorter $\lambda$ all increase tunneling probability — but smaller bandgap also increases ambipolar leakage and off-state current, and lighter mass materials often have lower density of states, limiting on-current from a different direction.

On-current in tunnel FETs is fundamentally lower than in MOSFETs at equivalent dimensions because tunneling transmission is less than unity. Even optimized homojunction silicon TFETs typically achieve on-currents of 1–10 µA/µm, compared to hundreds of µA/µm in MOSFETs at similar supply voltages. The tunneling probability, density of states at the junction, junction area, and electrostatic gate control over the tunneling region all limit current. Increasing on-current requires reducing the effective bandgap (heterojunction engineering), increasing tunneling area (vertical or line-tunneling architectures), improving gate electrostatics (thin body, gate-all-around), or combining multiple approaches — each adding fabrication complexity.

Heterojunction tunnel FETs use a smaller-bandgap material at the source to reduce the tunneling barrier and increase on-current. A type-II staggered or type-III broken-gap heterojunction — such as InAs/GaSb, InAs/Si, Ge/Si, or InGaAs/GaAsSb — reduces the effective tunneling bandgap below that of either constituent material. InAs/GaSb broken-gap junctions can achieve ~10× higher tunneling current than Si homojunctions because the tunneling distance approaches zero when valence and conduction bands overlap. However, these III-V heterojunctions introduce lattice mismatch, interface defects, complex epitaxy, and integration challenges with silicon CMOS.

Ambipolar conduction is an intrinsic consequence of the gated p-i-n structure. A tunnel FET with symmetric source and drain doping conducts current at both positive and negative gate biases — electrons tunnel at the source junction under positive $V_{GS}$, and holes tunnel at the drain junction under negative $V_{GS}$. This ambipolar current degrades the off-state, increases standby power, and complicates circuit design. Mitigation strategies include asymmetric source/drain doping profiles, gate-drain underlap (a 25 nm underlap in InAs/InGaAsSb/GaSb nanowire TFETs reduced minimum current from 92 pA/µm to 23 pA/µm), heterostructure drain barriers, and dual-gate architectures — all at the cost of additional process complexity and potential on-current reduction.

The tunneling junction must be atomically abrupt to maintain steep subthreshold swing. Dopant diffusion, intermixing, interface roughness, and defect states at the tunneling junction broaden the transition between tunneling and non-tunneling regimes. A source junction with a dopant gradient extending over 2–3 nm can degrade SS from sub-60 to 80–100 mV/decade by creating a distribution of tunneling distances rather than a single well-defined barrier. Achieving abrupt junctions requires low-temperature processing, in-situ doped epitaxy, molecular beam epitaxy (MBE), or atomic layer doping — techniques that are slower and more expensive than standard ion implantation.

Interface trap density at the gate-semiconductor boundary degrades subthreshold swing through the relation $SS = \ln(10) \cdot (kT/q) \cdot (1 + C_{it}/C_{ox})$. Even moderate trap densities of $10^{12}$ cm⁻² eV⁻¹ can push SS above 60 mV/decade regardless of the tunneling physics, because traps add a parasitic capacitance $C_{it} = qD_{it}$ that reduces gate efficiency. High-k gate dielectrics with EOT below 1.0 nm and interface-trap passivation achieving $D_{it}$ below $10^{11}$ cm⁻² eV⁻¹ are necessary conditions for sub-60 mV/decade operation — the same interface engineering challenges that advanced CMOS faces, amplified by the steep-slope requirement.

Trap-assisted tunneling (TAT) through defect states in the forbidden gap degrades both SS and off-current. Carriers can tunnel in two steps via a mid-gap trap rather than directly across the full bandgap, reducing the effective tunneling barrier. TAT current is proportional to trap density and depends weakly on gate voltage, creating a parallel leakage path that flattens the subthreshold slope. Defects at the heterojunction interface, in the high-k dielectric, and in the semiconductor bulk all contribute. Reducing TAT requires epitaxial quality approaching that of photonic devices, with dislocation densities below 10⁶ cm⁻² and point-defect concentrations below 10¹⁶ cm⁻³.

Line tunneling and vertical architectures increase the effective tunneling area beyond the cross-sectional junction footprint. In a conventional point-tunneling TFET, current flows laterally through the source-channel junction; the tunneling area is limited to the junction cross section. Line tunneling orients the tunneling direction perpendicular to the gate, so the entire gate-overlapped source region contributes. Vertical nanowire and nanosheet TFETs wrap the gate around the tunneling junction, improving electrostatic control and increasing tunneling area per footprint. These architectures require vertical epitaxy, selective area growth, or nanosheet release processes with sub-nanometer interface control.

Gate electrostatics must control the tunneling barrier more efficiently than in a MOSFET. The screening tunneling length $\lambda$ — which sets how quickly the bands bend at the junction — depends on body thickness, gate oxide thickness, dielectric constants, and geometry. Thinner bodies, thinner oxides, higher-k dielectrics, and gate-all-around geometries all reduce $\lambda$ and steepen the band bending. A double-gate TFET with 5 nm body thickness and 0.5 nm EOT can achieve $\lambda$ below 3 nm, enabling tunneling distances short enough for meaningful current. Single-gate planar TFETs with thicker bodies struggle to achieve sub-60 mV/decade SS because the gate cannot bend the bands sharply enough at the junction.

Silicon homojunction TFETs offer CMOS compatibility but suffer from the large indirect bandgap of 1.12 eV and heavy tunneling mass. The indirect gap requires phonon assistance for tunneling, which reduces the tunneling rate by orders of magnitude compared to direct-gap materials. Strained Si, SiGe alloys, and Ge (direct gap ~0.66 eV at $\Gamma$ point with 0.8 eV indirect gap) improve tunneling rates. Ge-source/Si-channel heterojunctions combine higher Ge tunneling rate with Si channel compatibility. However, Ge introduces interface passivation challenges, GeO₂ instability, and junction leakage that must be managed.

III-V materials offer direct bandgaps and light effective masses ideal for tunneling but face integration barriers with silicon. InAs ($E_g$ = 0.354 eV, $m^*$ = 0.023$m_0$), InGaAs (tunable gap), and GaSb ($E_g$ = 0.726 eV) have demonstrated the highest TFET on-currents. The InAs/GaSb broken-gap system eliminates the tunneling barrier entirely at the heterojunction, enabling high current density. Integration with silicon CMOS requires either heterogeneous integration (wafer bonding, transfer), selective area epitaxy on Si with buffer layers to manage lattice mismatch (6.1 Å for InAs/GaSb versus 5.43 Å for Si, a ~12% mismatch), or monolithic III-V-on-Si growth with threading dislocation density below 10⁷ cm⁻².

Two-dimensional materials (MoS₂, WSe₂, black phosphorus, and van der Waals heterostructures) offer atomically sharp interfaces and tunable bandgaps for TFET applications. The absence of dangling bonds at 2D/2D interfaces eliminates conventional interface traps, and the atomic thinness provides excellent gate control. MoS₂/black phosphorus and MoS₂/WSe₂ heterojunctions have demonstrated steep switching. However, 2D TFETs face challenges in contact resistance, doping control, large-area uniformity, and current density limited by the atomic-layer channel thickness.

Negative-capacitance tunnel FETs combine ferroelectric gate dielectrics with tunneling injection to amplify gate efficiency. A ferroelectric layer (HfZrO₂) in series with the gate dielectric provides voltage amplification through the negative-capacitance effect, effectively boosting the internal gate voltage beyond the applied voltage. This can steepen the subthreshold swing below what tunneling alone achieves and partially compensate for the on-current deficit. The approach requires stabilizing the ferroelectric in its negative-capacitance regime, avoiding hysteresis, and managing the additional thickness and process complexity of the ferroelectric layer.

Circuit design with tunnel FETs must account for asymmetric drive strength, unidirectional conduction, and Miller capacitance differences. Unlike MOSFETs, TFETs have asymmetric source and drain — reversing the device does not produce equivalent current. The $I_D$–$V_{DS}$ characteristic shows a delayed saturation region and superlinear onset that differs from MOSFET square-law behavior. These asymmetries affect logic gate design, signal integrity, analog performance, and standard-cell library development. SRAM cells, ring oscillators, and voltage references require TFET-specific topologies.

Read tunnel FET through a band-alignment, tunneling-probability, junction-abruptness, and defect-limited subthreshold swing lens rather than a low-power transistor scaling lens — steep slope is a necessary but not sufficient condition, and the device is only as good as the weakest link in its tunneling chain.

Following tunnel FET physics from band-to-band tunneling probability through heterojunction engineering, ambipolar suppression, gate electrostatics, interface quality, trap-assisted tunneling, and circuit-level asymmetry is the kind of device-physics-to-integration connection Chip Foundry Services makes explicit — turning quantum tunneling into a manufacturable steep-slope switch.

Start=>start: Select material system and tunneling architecture
Band=>operation: Engineer band alignment: homojunction, staggered, or broken-gap heterojunction
Junction=>operation: Form abrupt tunneling junction: epitaxy, in-situ doping, low-temperature processing
JuncCheck=>condition: Junction abruptness, defect density, and dislocation count pass?
Gate=>operation: Deposit high-k gate stack: EOT, D_it, electrostatic control over tunneling region
GateCheck=>condition: EOT, interface traps, and gate leakage within spec?
Ambipolar=>operation: Implement ambipolar suppression: underlap, asymmetric doping, drain barrier
IVCheck=>condition: SS, I_on, I_off, and I_on/I_off ratio meet targets?
TATCheck=>condition: Trap-assisted tunneling and defect leakage below threshold?
Circuit=>operation: Validate in TFET-specific circuit topologies: asymmetric drive, unidirectional
Release=>end: Release qualified tunnel FET
Hold=>end: Hold and investigate
Start->Band->Junction->JuncCheck
JuncCheck(yes)->Gate->GateCheck
JuncCheck(no)->Hold
GateCheck(yes)->Ambipolar->IVCheck
GateCheck(no)->Hold
IVCheck(yes)->TATCheck
IVCheck(no)->Hold
TATCheck(yes)->Circuit->Release
TATCheck(no)->Hold

Band-to-Band Tunneling Physics and the WKB Framework

The tunneling current in a TFET is governed by the quantum-mechanical transmission probability through the forbidden gap at the source junction. The WKB (Wentzel-Kramers-Brillouin) approximation provides the analytical framework: the transmission coefficient $T_{WKB}$ decreases exponentially with the product of tunneling distance, effective mass, and bandgap to the three-halves power. This exponential sensitivity means that small changes in any of these parameters produce large changes in current — a 10% reduction in effective bandgap can increase tunneling current by 2–5×, while a 1 nm increase in tunneling distance can reduce it by an order of magnitude.

The screening tunneling length $\lambda$ captures how effectively the gate bends the bands at the junction. For a double-gate geometry, $\lambda \approx \sqrt{(\epsilon_{ch}/\epsilon_{ox}) \cdot t_{ch} \cdot t_{ox}/4}$, where $\epsilon_{ch}$ and $\epsilon_{ox}$ are the channel and oxide permittivities, and $t_{ch}$ and $t_{ox}$ are the channel body thickness and oxide thickness. Reducing $\lambda$ below 5 nm requires body thickness below 10 nm, EOT below 1.0 nm, and high-k dielectrics — the same scaling vectors as advanced CMOS but with even tighter requirements because tunneling transmission depends on $\lambda$ exponentially rather than linearly.

Direct-gap tunneling is orders of magnitude more efficient than indirect-gap phonon-assisted tunneling. In silicon, the conduction-band minimum is at the X-valley, so BTBT requires a phonon to conserve momentum, reducing the tunneling rate by a factor of 100–1000 compared to a direct-gap material of similar bandgap. Germanium has an indirect gap of 0.66 eV but its direct gap at the $\Gamma$ point is only 0.8 eV, and strain can reduce this further. III-V materials such as InAs (0.354 eV direct gap) and InGaAs (tunable) provide direct tunneling without phonon mediation, which is why they dominate high-performance TFET research despite integration complexity.

Heterojunction Engineering and Material Integration

Type-II staggered and type-III broken-gap heterojunctions reduce the effective tunneling barrier below the bandgap of either constituent. In a type-II junction (e.g., InGaAs/GaAsSb), the source valence band sits above the channel conduction band by less than either material's bandgap, reducing the tunneling distance. In a type-III broken-gap junction (e.g., InAs/GaSb), the source valence band overlaps the channel conduction band, creating a zero-thickness tunneling barrier at the band crossing. The broken-gap system offers the highest tunneling rates but also the highest ambipolar leakage because the drain side can also form a broken-gap alignment under reverse bias.

Trap-assisted tunneling through mid-gap defect states creates a gate-voltage-independent leakage floor that obscures steep switching. Carriers tunnel from the source to a defect state within the bandgap, then from the defect to the channel — a two-step process with lower barrier than direct BTBT. TAT current depends on defect density and energy position but responds weakly to gate voltage, creating a leakage current that appears as a parallel path in the subthreshold region. The steep-slope advantage of BTBT is visible only above this TAT floor, which in practice limits the useful sub-60 mV/decade range to 1–3 decades of current in most fabricated devices.

Reducing TAT requires semiconductor crystal quality approaching photonic-grade material. Threading dislocation density below 10⁶ cm⁻², point-defect concentration below 10¹⁶ cm⁻³, and interface-trap density below 10¹¹ cm⁻² eV⁻¹ are baseline requirements. For heterojunction TFETs, the critical interface is the tunneling junction itself, where every defect within the tunneling distance acts as a TAT center. Lattice-matched or pseudomorphic growth, in-situ surface preparation, and low-temperature post-processing help preserve junction quality.

Architectures, Gate Electrostatics, and Scaling Toward Manufacture

Vertical nanowire and nanosheet TFET architectures improve gate control and tunneling area per unit footprint. A gate-all-around nanowire with 5–8 nm diameter provides near-ideal electrostatic control ($\lambda$ below 3 nm) and enables line tunneling along the entire gate-overlapped source region. Vertical orientation decouples tunneling length from lithographic patterning — the junction is defined by epitaxial layer thickness rather than gate length. IMEC, Intel, TSMC, Samsung, and academic groups at MIT, UC Berkeley, UC Santa Barbara, and ETH Zurich have demonstrated nanowire and nanosheet TFET prototypes in Si, Ge, InAs, InGaAs, and 2D materials.

Negative-capacitance boosting with ferroelectric HfZrO₂ gate dielectrics can amplify internal gate voltage and steepen the subthreshold swing beyond the intrinsic TFET limit. The ferroelectric layer provides a voltage gain $A_V = C_{FE}/(C_{FE} - C_{MOS})$ when stabilized in its negative-capacitance regime, effectively multiplying the applied gate voltage. Combined with tunneling injection, NC-TFETs have demonstrated SS below 10 mV/decade over limited current ranges. The challenges are ferroelectric thickness and composition control, hysteresis avoidance, reliability under bias stress, and integration with the already-complex TFET gate stack.

Qualifying a tunnel FET process requires metrology that resolves sub-nanometer junction profiles and single-decade current characteristics. Atom probe tomography (APT) maps 3D dopant distributions with near-atomic resolution. Secondary ion mass spectrometry (SIMS) profiles dopant concentration versus depth. Scanning tunneling spectroscopy (STS) measures local density of states at the tunneling junction. Electrical characterization must capture the full $I_D$–$V_{GS}$ curve with sub-picoamp resolution, fast measurement to avoid charge-trapping artifacts, and temperature-dependent extraction to separate BTBT from TAT components.