Turn-on time is the speed at which an ESD protection clamp transitions from its off-state to its low-impedance on-state when an electrostatic discharge event occurs — a critical parameter because ESD pulses rise in as little as 100 picoseconds (CDM), and any delay in clamp activation allows destructive voltage overshoot at the protected circuit.

What Is Turn-On Time?

• Definition: The time interval between the arrival of an ESD transient at the clamp and the point where the clamp reaches its full conducting state, measured from the voltage exceeding the trigger threshold to the current reaching its steady-state ESD level.
• Voltage Overshoot: During the turn-on delay, voltage at the protected node continues to rise beyond the steady-state clamping voltage — this overshoot can exceed oxide breakdown even if the final clamping voltage is safe.
• ESD Pulse Rise Times: HBM pulses rise in approximately 2-10 ns, CDM pulses rise in 100-250 ps, and system-level ESD (IEC 61000-4-2) rises in less than 1 ns.
• Design Target: The clamp must turn on faster than the ESD pulse rise time to prevent voltage overshoot at the protected gate oxide.

Why Turn-On Time Matters

• CDM Protection: Charged Device Model events have sub-nanosecond rise times — a clamp that takes 5 ns to turn on provides zero CDM protection because the oxide ruptures during the overshoot.
• Advanced Node Sensitivity: Gate oxides at 7nm and below have breakdown voltages under 5V with extremely low energy-to-failure — even brief sub-nanosecond overshoot can cause permanent damage.
• Voltage Overshoot Calculation: Peak overshoot ≈ L_parasitic × (dI/dt), where L is the parasitic inductance of the clamp interconnect and dI/dt is the ESD current slew rate.
• First Peak Failure: Many ESD failures occur during the "first peak" of the voltage waveform before the clamp fully activates — turn-on time directly determines first peak magnitude.
• Multi-Stage Delay: In multi-stage I/O protection, the cumulative delay through primary and secondary stages must still be faster than the ESD pulse rise time.

Turn-On Time by Clamp Type

Design Techniques for Fast Turn-On

• Fast RC Trigger: Design RC networks with small time constants (100-500 ps) using MOS capacitors and short poly resistors for rapid dV/dt detection.
• Cascaded Inverter Trigger: Use fast logic gates (2-3 cascaded inverters) to detect ESD transients and drive the clamp MOSFET gate — achieves sub-nanosecond triggering.
• Diode-Triggered SCR: Add a diode trigger chain to an SCR to bypass its slow regenerative turn-on with a fast external trigger.
• Layout Optimization: Minimize parasitic inductance and resistance in the clamp's current path through wide metal connections, multiple vias, and short routing.
• Multi-Finger Design: Use many narrow fingers rather than few wide fingers to reduce distributed RC delay across the device width.

Measurement Techniques

• VF-TLP: Very Fast Transmission Line Pulse testing with 100-300 ps rise time pulses directly measures the clamp's transient response and voltage overshoot.
• TDR: Time Domain Reflectometry characterizes the impedance transition during clamp turn-on.
• On-Chip Sensors: Some test chips include on-chip voltage sensors to capture the actual transient waveform during ESD events.

Turn-on time is the race between destruction and protection — in modern ICs where oxides can fail in picoseconds, designing clamps that respond faster than the ESD threat is the difference between a chip that survives handling and one that dies at first touch.