UPF (Unified Power Format, IEEE 1801) is the standardized specification language for describing the power intent of an integrated circuit — defining power domains, supply networks, isolation cells, level shifters, retention registers, and power state transitions in a format that is understood by all EDA tools across the design flow from RTL simulation through synthesis, place-and-route, and verification, ensuring that multi-voltage power management is correctly implemented from specification to silicon.

Why UPF Is Needed

• Modern SoCs have 5-20+ power domains with different voltages and shutdown capabilities.
• Power intent affects RTL behavior (isolation, retention) but is NOT expressed in RTL code.
• Without UPF: Each EDA tool would need separate power specifications → inconsistency → silicon bugs.
• With UPF: Single source of truth for power architecture → all tools consistent.

Key UPF Constructs

Power Domain Example

# Define always-on domain
create_power_domain PD_AON -include_scope
create_supply_net VDD_AON -domain PD_AON
create_supply_net VSS     -domain PD_AON

# Define switchable GPU domain
create_power_domain PD_GPU -elements {gpu_top}
create_supply_net VDD_GPU -domain PD_GPU
set_domain_supply_net PD_GPU -primary_power_net VDD_GPU -primary_ground_net VSS

# Power switch for GPU domain
create_power_switch GPU_SW \
  -domain PD_GPU \
  -input_supply_port {vin VDD_AON} \
  -output_supply_port {vout VDD_GPU} \
  -control_port {gpu_pwr_en} \
  -on_state  {on_s  vin {gpu_pwr_en}} \
  -off_state {off_s {!gpu_pwr_en}}

Isolation Strategy

• When a power domain shuts down, its outputs go to undefined state (X).
• Isolation cells clamp these signals to known values (0, 1, or latched value).
• Placed at every output crossing from switchable domain to always-on domain.

Retention Strategy

• Retention registers: Special flip-flops with balloon latch powered by always-on supply.
• Before power-down: SAVE signal copies main latch state to balloon latch.
• After power-up: RESTORE signal copies balloon latch back to main latch.
• Cost: ~30-50% larger than standard flip-flop.

Power State Table

EDA Flow Integration

• RTL simulation: UPF-aware simulator corrupts signals from off domains → catch missing isolation.
• Synthesis: Insert isolation cells, level shifters, retention registers per UPF.
• P&R: Place power switches, route supply nets, check always-on routing.
• Signoff: Verify all power states, check supply integrity, validate state transitions.

UPF is the language that turns power management from ad-hoc implementation into systematic engineering — without a formal power intent specification, the dozens of tools and hundreds of engineers involved in modern SoC development would have no consistent way to implement, verify, and validate the complex multi-voltage architectures that deliver the 10-100× power range modern chips require.