UPF (Unified Power Format) is the IEEE 1801 industry standard for specifying power intent in integrated circuit designs — providing a structured, Tcl-based language to define power domains, supply networks, power switches, isolation, retention, level shifters, and power states that drive the entire low-power implementation and verification flow.

UPF Key Commands

• create_power_domain: Define a power domain and assign logic elements:

`` create_power_domain CORE -elements {cpu_top} create_power_domain AON -elements {pmu wakeup_ctrl} ``

• create_supply_port / create_supply_net: Define power supply connections:

`` create_supply_port VDD -direction in create_supply_net VDD_core -domain CORE ``

• create_power_switch: Define power gating switches:

`` create_power_switch core_sw \ -domain CORE \ -input_supply_port {vddin VDD} \ -output_supply_port {vddout VDD_core} \ -control_port {sleep pmu/core_sleep} \ -on_state {on_state vddin {!sleep}} ``

• set_isolation: Specify isolation at domain boundaries:

`` set_isolation iso_core \ -domain CORE \ -isolation_power_net VDD_aon \ -clamp_value 0 \ -applies_to outputs set_isolation_control iso_core \ -domain CORE \ -isolation_signal pmu/iso_core \ -isolation_sense high ``

• set_retention: Specify retention for flip-flops:

`` set_retention ret_core \ -domain CORE \ -retention_power_net VDD_aon \ -save_signal {pmu/save_core high} \ -restore_signal {pmu/restore_core high} ``

• set_level_shifter: Specify level shifting requirements:

`` set_level_shifter ls_core_to_io \ -domain CORE \ -applies_to outputs \ -rule both ``

UPF Power States

• add_power_state: Define the set of valid power modes:

`` add_power_state CORE \ -state {ACTIVE -supply_expr {VDD_core == FULL_ON}} \ -state {SLEEP -supply_expr {VDD_core == OFF}} ``

UPF Versions

• UPF 1.0: Basic power domain, isolation, retention, level shifter specification.
• UPF 2.0 (IEEE 1801-2009): Added supply states, power state tables, refined semantics.
• UPF 2.1 (IEEE 1801-2013): Added successive refinement — allows UPF to be progressively detailed from architecture to implementation.
• UPF 3.0+: Continued evolution with enhanced modeling capabilities.

UPF in Practice

• UPF files are written early in the design process — at the architecture/RTL stage.
• All major EDA tools read UPF: Synopsys (Design Compiler, ICC2, PrimeTime), Cadence (Genus, Innovus, Tempus), Siemens (Questa).
• UPF is the de facto standard across the industry — supported by all major foundries, IP providers, and design teams.

UPF is the common language of low-power IC design — it enables a unified specification that drives synthesis, place-and-route, verification, and sign-off, ensuring consistent power architecture implementation throughout the flow.