A vertical transistor turns the current path on its side relative to a conventional planar or lateral gate-all-around device: instead of carriers flowing horizontally between a source and drain that sit side by side on the wafer surface, they flow up or down through a channel that stands perpendicular to the wafer plane, with source and drain stacked as a bottom and top pillar contact. That single geometric change decouples device footprint from channel length in a way no lateral architecture can match, because the channel length is now set by how tall the pillar is etched or grown rather than by how tightly a lithography tool can print two side-by-side features, which is precisely the constraint that lateral nanosheet and forksheet scaling are running up against. The tradeoff is that every step of the flow — pillar formation, gate wrap, and top/bottom contact — must now be executed inside or around a narrow, tall structure instead of on an open, flat surface, so vertical integration exchanges a lithography-resolution problem for a high-aspect-ratio process-control problem.

Because current flows vertically, a vertical transistor's footprint on the wafer is set by the pillar pitch rather than by the sum of gate length, spacer width, and source/drain length that determines a lateral device's footprint. A lateral gate-all-around transistor still has to lay out its full channel-plus-junction length end to end along the wafer surface, but a vertical transistor folds that same length upward into the third dimension, so shrinking the pillar diameter and pitch — not the channel length — becomes the primary lever for area scaling, decoupling density gains from the aggressive channel-length shrinks that have driven most of CMOS scaling since the 1990s.

A vertical channel pillar is typically formed either by anisotropic etching of a blanket epitaxial layer down to a target diameter, or by selective bottom-up epitaxial growth through a patterned dielectric template, and the choice between the two shapes every downstream process step. Etched pillars inherit whatever crystal quality the starting epitaxial film had, while selectively grown pillars can in principle start from a cleaner nucleation surface but must control lateral facet formation and diameter uniformity as growth proceeds upward, and either route has to hold pillar diameter uniformity tight enough — commonly within about 1 nm to 2 nm across a wafer — that threshold voltage does not vary device to device.

A vertical gate-all-around structure wraps a ring or sleeve of gate dielectric and metal completely around the pillar's circumference, and because the gate length is now defined by a deposited or etched vertical spacer thickness rather than by a lithographically printed line, it can in principle be controlled to sub-nanometer precision independent of the lithography tool's resolution limit. This decoupling is one of the most attractive properties of the vertical architecture: a spacer-defined gate length of, say, 15 nm to 20 nm can be set by a deposition or etch-back step with tight thickness control, rather than by the printing and trimming steps a lateral device needs to hit the same target.

Source and drain in a vertical transistor sit at the top and bottom of the pillar rather than side by side, which relieves lateral spacing constraints but introduces a distinct set of isolation and contact problems: the bottom junction must be electrically isolated from the substrate and from neighboring pillars, and the top contact must land precisely on a pillar cap only a few nanometers across without shorting to the gate stack immediately below it. Self-aligned contact schemes, borrowed conceptually from the spacer-defined contact modules already used in lateral finFET and nanosheet flows, are the standard way to keep the top contact from overlapping the gate, but the margin for misalignment shrinks as pillar diameter shrinks toward 5 nm.

Parasitic capacitance and contact resistance both scale differently in a vertical device than in a lateral one, because the gate now wraps a much larger fraction of the total S/D-to-gate overlap area per unit channel length, and the top and bottom contacts each present a small, high-resistance interface area that pushes contact resistivity into the picture as a first-order performance limiter. Reported research contact resistivities for advanced vertical and lateral GAA test structures fall in the ballpark of a few hundred ohm·µm² or lower, and hitting that target inside a pillar's top and bottom cap — rather than across an open, easily silicided lateral junction — is one of the harder unsolved problems in vertical device engineering.

Electrostatic control in a vertical gate-all-around device is comparable to a lateral nanosheet's, since both wrap gate metal fully around the channel cross-section, but the vertical geometry gives a designer an additional lever: gate length can be tuned independently of footprint simply by growing or etching a taller or shorter pillar, whereas a lateral device's gate length is tied directly to the chip area it consumes. That independence matters most for suppressing short-channel effects like drain-induced barrier lowering and subthreshold leakage, where a subthreshold swing close to the thermal limit of about 60 mV/decade at room temperature — and reported vertical GAA research devices in the 65 mV/decade to 75 mV/decade range — depends on the gate maintaining tight electrostatic control over the full channel length regardless of how that length was set.

Vertical transistor fabrication flow ──▶ pillar → gate wrap → isolate → contact
  Blanket epitaxial channel growth (Si or III-V, MBE/MOCVD)
       │      starting material for etched-pillar route
       │
       ├─▶ pillar definition (anisotropic etch or selective bottom-up epi)
       │      target diameter ≈5-15 nm, aspect ratio up to 1:20
       │
       ├─▶ conformal ALD gate dielectric + metal wrap
       │      EOT ≈1.0-1.2 nm, step coverage near 100 percent
       │
       ├─▶ spacer-defined gate length + bottom junction isolation
       │      gate length ≈15-20 nm set by spacer thickness
       │
       ├─▶ self-aligned top contact formation on pillar cap
       │      contact resistivity target: few hundred Ω·µm²
       │
       └─▶ metrology + electrical qualification
              subthreshold swing target ≈65-75 mV/decade

Density scaling in a vertical architecture reduces, to first order, to how tightly pillars can be packed on a 300 mm wafer, since the transistor's chip-area footprint is roughly the pillar pitch squared rather than a function of gate length at all. Shrinking pillar pitch from around 30 nm to something closer to 20 nm nearly doubles areal transistor density on paper, which is why vertical architectures are discussed as a scaling path that could extend density gains past the point where lateral nanosheet and forksheet pitch scaling runs into lithography-driven diminishing returns.

The semiconductor memory industry has already solved a version of this high-aspect-ratio scaling problem at enormous volume in 3D NAND flash, where SK hynix, Samsung, and other memory makers routinely etch and fill channel holes with aspect ratios well beyond 1:40 across more than 200 stacked layers, and vertical-transistor logic research draws directly on etch, ALD, and metrology techniques refined in that memory context. The physics and device targets differ sharply — 3D NAND channel holes carry charge-storage cells rather than a switching logic channel — but the shared process toolkit, particularly deep-trench ALD conformality and high-aspect-ratio plasma etch control, is one reason equipment suppliers active in memory scaling are also central to vertical logic-transistor development.

Research and process-equipment activity on vertical transistor structures spans academic device physics groups, foundry research divisions, and the deposition and etch tool suppliers whose equipment must be re-qualified at each new aspect ratio. imec has published extensively on vertical and stacked-nanosheet device architectures as part of its post-nanosheet scaling roadmap, TSMC and Intel both maintain internal research tracks evaluating vertical and CFET-adjacent structures, and equipment suppliers including Applied Materials, Lam Research, and ASM develop the high-aspect-ratio etch and ALD tools that any vertical-device flow depends on, while IBM and academic groups have published foundational vertical MOSFET device physics going back well over a decade.

The economics of adopting a vertical architecture hinge on whether the density gain from pillar-pitch scaling outweighs the added cost of high-aspect-ratio process modules that a lateral nanosheet flow does not need, since every additional ALD and etch qualification step at tighter aspect ratio adds cycle time and tool cost per wafer. A fab evaluating vertical transistors has to weigh area scaling benefit against a real increase in process complexity, which is why most public roadmaps treat vertical architectures as a longer-horizon option layered in alongside, rather than immediately replacing, lateral nanosheet and forksheet scaling.

Fabrication tolerances for a production vertical transistor are unusually unforgiving because a single narrow pillar carries the entire device's current, so a pillar-diameter variation that a wide lateral channel would simply average across instead directly shifts threshold voltage and drive current for that individual device. Wafer-level pillar-diameter uniformity within roughly 1 nm to 2 nm, combined with ALD step-coverage close to 100 percent from top to bottom of the trench, is treated as a first-order yield requirement in a way that a conventional lateral finFET or nanosheet line, built around statistically averaged channel width, does not need to consider.

The forksheet, gate-all-around, junctionless, carbon-nanotube, graphene, single-electron-transistor, and quantum-dot-transistor architectures each modify or replace a lateral channel while keeping current flow parallel to the wafer surface; the vertical transistor instead reorients the entire current path, which is why its fabrication priorities diverge from nearly every other device discussed alongside it. A lateral scaling innovation is judged by how tightly it can be printed and trimmed on an open surface; a vertical transistor is judged by how uniformly it can be etched, grown, coated, and contacted inside a narrow, tall trench, and none of those process steps can be qualified in isolation from pillar diameter, gate-wrap conformality, and contact placement together. Read vertical transistor structures through a coupled-systems lens: pillar diameter, aspect-ratio process control, gate-wrap conformality, and top/bottom contact placement do not improve independently, so a vertical transistor only delivers its promised density gain when etch, deposition, and contact modules are all qualified together against the same aspect ratio that motivated turning the channel on its side in the first place.

Appendix: Process Control and Metrology Reference

Cross-sectional transmission electron microscopy remains the standard technique for directly confirming pillar diameter, gate-wrap conformality, and top/bottom contact alignment inside a completed vertical transistor, since optical metrology generally cannot resolve or penetrate a 5 nm to 15 nm diameter feature buried inside a high-aspect-ratio stack. Because TEM cross-sectioning is destructive and slow, it is typically reserved for process qualification and periodic sampling rather than every-wafer inline monitoring, leaving faster but less direct electrical proxies, such as threshold-voltage distribution across a wafer, as the primary day-to-day production control signal.

Electrical test structures distributed across a wafer, tracking threshold voltage, subthreshold swing, and on-current across many nominally identical vertical pillars, are the practical way a fab detects pillar-diameter drift or gate-wrap non-conformality without resorting to destructive cross-sectioning on every lot. A tight threshold-voltage distribution, commonly targeted within a spread of about 20 mV to 30 mV across a 300 mm wafer, is treated as indirect confirmation that pillar geometry and gate-stack thickness are holding within their process window.

Academic and industrial research on vertical transistor structures continues to focus on three coupled fronts: pushing pillar diameter down while holding mobility and defect density steady, extending ALD conformality to even higher aspect ratios as pillar height increases, and developing lower-resistance top and bottom contact schemes that do not require sacrificing pillar diameter to make room for contact area. Progress on any one front in isolation delivers little practical benefit unless matched by progress on the other two, which is the central reason vertical-transistor development is tracked as an integrated process-module problem rather than a series of independent point improvements.