Via resistance is the electrical resistance encountered by current flowing vertically between adjacent metal interconnect levels through a conductive plug, encompassing the bulk resistivity of the core fill, the higher-resistivity diffusion barrier and adhesion liner, and the interfacial contact resistance at the top and bottom metal boundaries. In advanced technology nodes where line widths and via diameters scale below 20 nanometers, via resistance rises exponentially as bulk electron mean free path effects, grain boundary scattering, and liner thickness scaling limits squeeze the conductive cross-section. Understanding and optimizing via resistance is critical because vertical vias now contribute more than half of the total back-end-of-line (BEOL) resistance-capacitance (RC) delay, directly constraining clock frequency, increasing dynamic power dissipation, and determining circuit reliability under high current density electromigration stress.

Total via resistance combines bulk conductor transport with non-negligible interfacial barrier resistance. The total resistance across a dual-damascene vertical via is formally expressed as the series combination of bulk plug resistance, barrier and liner sidewall resistance, and the contact interface resistances at the upper and lower metal boundaries:

where $h_{\text{via}}$ is the via height, $A_{\text{eff}}$ is the effective cross-sectional area of the core conductor, $\rho_{\text{eff}}$ is the size-dependent effective bulk resistivity, and $\rho_c$ is the specific contact resistivity in $\Omega\cdot\text{cm}^2$. While bulk resistivity dominates in wide interconnects, interfacial contact resistivity $\rho_c$ and liner displacement dominate at advanced nodes, scaling inversely with the square of the via diameter ($1/d^2$).

Electron scattering at surfaces and grain boundaries causes severe resistivity escalation at sub-20nm dimensions. In bulk copper, the electron mean free path is approximately $\lambda_0 \approx 39\text{ nm}$ at room temperature. When the physical via diameter falls below this mean free path, specular reflection breaks down, and resistivity surges according to the combined Fuchs-Sondheimer surface scattering and Mayadas-Shatzkes grain boundary scattering relations:

where $p$ is the surface specularity parameter ($p=0$ for diffuse scattering), $g$ is the average grain size (which scales down with via width), and $R_g$ is the grain boundary reflection coefficient ($R_g \approx 0.2\text{--}0.4$). Consequently, the effective resistivity of copper inside a 12 nm via exceeds $15\text{--}20\ \mu\Omega\cdot\text{cm}$, more than an order of magnitude higher than bulk copper ($1.68\ \mu\Omega\cdot\text{cm}$).

Barrier and liner thickness limits accelerate cross-sectional area starvation in conventional copper vias. Copper readily diffuses into silicon oxide and low-k dielectrics under thermal and electrical stress, causing catastrophic dielectric leakage and breakdown. To prevent diffusion, conventional vias require a conformal tantalum nitride (TaN) diffusion barrier and a cobalt (Co) or ruthenium (Ru) wetting liner with a combined thickness of $2.5\text{--}3.5\text{ nm}$. Because this barrier envelope does not scale proportionally with feature pitch, the remaining core conductor area drops precipitously: in a 14 nm via, a 3 nm barrier/liner stack consumes more than $65\%$ of the total cross-sectional volume, leaving an effective conductive core of only 8 nm diameter.

Alternative binary and elemental metals eliminate barriers to deliver a crossover in net via resistance. Elemental metals such as Ruthenium (Ru), Molybdenum (Mo), and Tungsten (W) exhibit significantly shorter electron mean free paths ($\lambda_{\text{Ru}} \approx 6.6\text{ nm}$, $\lambda_{\text{Mo}} \approx 5.5\text{ nm}$) and high cohesive energies that inherently resist atomic electromigration and dielectric diffusion without requiring a thick TaN barrier. Although bulk ruthenium ($\rho_0 \approx 7.1\ \mu\Omega\cdot\text{cm}$) has higher resistivity than bulk copper, its barrierless deposition allows $100\%$ of the via volume to carry current, producing a decisive resistance advantage over copper at via critical dimensions below $12\text{--}14\text{ nm}$.

Via bottom pre-clean and selective liner metallurgy govern interface contact resistivity. In standard dual-damascene processing, etch residues and polymer fluorocarbons deposit at the bottom of the via trench after dielectric reactive ion etching (RIE). If unremoved, these residues form high-resistance dielectric sub-layers with specific contact resistivities exceeding $10^{-8}\ \Omega\cdot\text{cm}^2$. Advanced manufacturing employs low-damage hydrogen or helium plasma pre-cleans combined with selective chemical vapor deposition (CVD) or atomic layer deposition (ALD) of cobalt or ruthenium caps to achieve clean metal-to-metal contact with specific contact resistivities below $10^{-9}\ \Omega\cdot\text{cm}^2$.

Via chain test structures and transmission line models provide statistical verification of fab-wide yield and resistance distributions. Direct four-terminal Kelvin test structures isolate the resistance of a single isolated via, while serpentine via chains containing $10^4$ to $10^6$ alternating metal-via-metal links verify parametric contact uniformity and stochastic yield across 300 mm wafers. Resistance distribution tails and bimodal distributions indicate localized liner pinching, incomplete pre-clean, or stress-induced voiding under thermal cycling, guiding statistical process control (SPC) and design-for-manufacturability (DFM) rules such as redundant via insertion.

st=>start: Define target BEOL node, via height, and metal pitch
clean=>operation: Run low-damage plasma pre-clean to strip fluorocarbon RIE residues
liner=>operation: Deposit conformal barrier/liner or prepare barrierless Ru/Mo interface
fill=>operation: Perform bottom-up superfilling electroplating or ALD metal deposition
cmp=>operation: Chemical mechanical planarization (CMP) to remove overburden
test=>condition: Single-via Kelvin and million-via chain resistance within target spec?
opt=>operation: Optimize pre-clean bias, liner thickness, and thermal reflow parameters
rel=>operation: Perform high-temperature electromigration stress test (EM Jmax validation)
pass=>end: Qualified low-resistance, high-reliability interconnect via standard
st->clean->liner->fill->cmp->test
test(yes)->rel->pass
test(no)->opt->clean

Designing advanced interconnects requires treating vertical via resistance not as an isolated parasitic but as an integrated material-barrier-and-interface-transport lens. As technology scaling drives logic architectures into backside power delivery networks (BSPDN) and nanosheet cell heights below 100 nm, vertical vias dictate whether theoretical transistor speed translates into real-world chip performance. Defensible via engineering couples accurate quantum confinement and grain boundary scattering physics with atomic-layer deposition control, redundant layout topology, and strict electromigration lifetime validation.