Via Formation — creating vertical metal connections between adjacent wiring layers, enabling the 3D wiring network that connects billions of transistors through 10–15 metal layers.

Types of Vias

• Standard via: Connects metal layer N to metal layer N+1. Square or rectangular
• Stacked via: Multiple vias directly on top of each other through several layers
• Via bar/pillar: Elongated via for lower resistance on critical paths
• Super via (skip via): Connects non-adjacent metal layers directly (skips levels). Saves routing resources

Via in Dual Damascene

1. Via-first approach: Etch via hole → etch trench → fill both simultaneously with Cu 2. Trench-first approach: Etch trench → etch via through trench bottom → fill 3. Via-first is more common at advanced nodes

Via Resistance

• Via resistance = $\rho \cdot h / A$ (resistivity × height / area)
• At advanced nodes: A single via can be 5–20Ω
• Multiple vias in parallel reduce resistance: Standard practice for critical nets

Design Rules

• Minimum via size and spacing defined by DRC
• Via enclosure: Metal must extend beyond via edges
• Redundant vias: Add extra vias for reliability (electromigration, manufacturing defects)

Scaling Challenges

• Via area shrinks → resistance increases
• Barrier liner takes larger fraction of via area
• Via misalignment to metal below becomes critical

Vias are the vertical highways of the interconnect stack — their resistance and reliability directly impact chip performance and yield.