Voltage Droop and Power Supply Noise is the transient voltage reduction on the chip's internal power grid that occurs when circuit switching activity changes suddenly — caused by the di/dt (rate of current change) through the parasitic inductance of the power delivery network (PDN) from the voltage regulator through the package to the die, where a typical droop of 50-100mV on a 0.75V supply (7-13%) directly reduces transistor drive current and can cause timing violations or logic errors if not properly mitigated.

Droop Physics

• Ohm's law: V_droop = L × di/dt + R × I
• L = total inductance (package pins + planes + on-die) ≈ 10-100 pH.
• di/dt: Sudden current change when many circuits switch simultaneously.
• Example: 100A current spike in 1ns through 50pH → V = 50pH × 100A/1ns = 5V!
• In practice: Distributed L and C filter the spike → droop is 50-150mV, lasting 10-100ns.

Droop Events

PDN Impedance Target

 Z_target = V_supply × ripple% / I_max
 
 Example: 0.75V supply, 5% allowed ripple, 100A max current
 Z_target = 0.75 × 0.05 / 100 = 375 µΩ
 
 This impedance must be maintained from DC to ~1GHz!

PDN Structure

<svg viewBox="0 0 494 131" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="494" height="131" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9"> VRM </tspan><tspan fill="#6e7681">──→</tspan><tspan fill="#c9d1d9"> [Board] </tspan><tspan fill="#6e7681">──→</tspan><tspan fill="#c9d1d9"> [Package] </tspan><tspan fill="#6e7681">──→</tspan><tspan fill="#c9d1d9"> [On-die power grid]</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">  12V</tspan><tspan fill="#6e7681">→</tspan><tspan fill="#c9d1d9">1V   Board cap    Pkg cap     On-die decap</tspan></text><text xml:space="preserve" x="20" y="69.7"><tspan fill="#c9d1d9">           (µF range)   (nF range)  (pF range)</tspan></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9">  </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9"> Slow    </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9"> Medium     </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9"> Fast      </tspan><tspan fill="#6e7681">↑</tspan><tspan fill="#c9d1d9"> Fastest</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#c9d1d9">  (µs)      (100ns)      (10ns)      (1ns)</tspan></text></g></svg>

• Each level handles different frequency range of current transients.
• Board capacitors: Handle slow transients (µs).
• Package decaps: Handle medium-speed transients (10-100ns).
• On-die decaps: Handle fast transients (1-10ns) — most critical for droop.

Droop Mitigation Strategies

Guardband Impact

• Design must work at V_min = V_supply - V_droop.
• 100mV droop on 750mV supply → design for 650mV → ~15% frequency loss.
• Reducing droop by 50mV → raise frequency by ~8% → significant performance gain.
• Every mV of droop reduction translates directly to performance or power savings.

Simulation and Signoff

• Dynamic IR drop analysis: Simulate power grid with time-varying current.
• Tools: Ansys RedHawk-SC, Cadence Voltus → compute worst-case droop at every node.
• VCD-based: Use simulation vectors → realistic switching patterns → accurate droop prediction.
• Vectorless: Statistical estimation → faster but conservative.

Voltage droop is the invisible performance thief in modern processor design — the guardbands that designers add to handle worst-case droop events directly subtract from achievable frequency, making PDN design and droop mitigation one of the highest-leverage optimizations for high-performance chips, where reducing voltage droop by even 10-20mV through better decoupling, power delivery, and di/dt management translates directly into measurable frequency and power efficiency improvements.