A voltage island is a physically isolated region of the chip that operates at a different supply voltage than its neighbors — enabling multi-VDD design where each functional block runs at the optimal voltage for its performance and power requirements.

Why Voltage Islands?

• Not all blocks on a chip need the same performance level. Running everything at the highest voltage wastes power on blocks that don't need that speed.
• Power scales quadratically with voltage: $P_{dynamic} \propto V_{DD}^2$. Reducing voltage by 20% reduces dynamic power by ~36%.
• Voltage islands allow each block to run at the minimum voltage that meets its performance target — maximizing power efficiency across the chip.

Voltage Island Architecture

• Separate Supply Rails: Each island has its own VDD distribution network — physically isolated from other islands' power grids.
• Independent Regulation: Each island may have its own voltage regulator (on-die LDO or external PMIC channel) to provide the specific voltage.
• Level Shifters at Boundaries: Every signal crossing between islands at different voltages needs a level shifter to convert signal levels.

Voltage Island Examples

• High-Performance CPU Core: 0.9V — needs maximum speed.
• DSP Block: 0.75V — moderate performance, optimized for efficiency.
• Control Logic: 0.65V — low speed requirements, minimum power.
• I/O Ring: 1.8V or 3.3V — fixed by interface standards.
• Always-On PMU: 0.5V — ultra-low voltage for minimum leakage.

Static vs. Dynamic Voltage Islands

• Static Voltage Islands: Each island operates at a fixed voltage, set during design. Different blocks at different fixed voltages.
• Dynamic Voltage Islands (DVFS): The voltage of an island can be changed at runtime based on workload — high voltage for demanding tasks, low voltage for idle or light workloads. Requires voltage regulators with dynamic output capability.

Physical Design Challenges

• Power Grid Isolation: Each island needs its own complete power grid — VDD routing must be physically separated between islands.
• Floorplanning: Islands should be contiguous, rectangular regions for clean power grid implementation.
• Level Shifter Placement: Level shifters at island boundaries consume area and add delay — must be accounted for in timing.
• Decoupling: Each island needs its own decoupling capacitance for supply stability.
• Electromigration: Different voltages mean different current densities — EM analysis must be per-island.

Voltage Island in UPF

create_power_domain CPU -elements {cpu_core}
create_supply_net VDD_CPU -domain CPU
set_level_shifter ls_cpu_to_ctrl -domain CPU \
  -applies_to outputs -rule both

Voltage islands are a cornerstone of power-efficient SoC design — they enable each block to operate at its optimal voltage, collectively reducing total chip power by 20–40% compared to single-VDD designs.