Patterned Wafer Inspection is the automated optical or e-beam scanning of wafers after circuit patterns have been printed and etched, using die-to-die or die-to-database image comparison algorithms to detect process-induced defects against the complex background of intentional circuit features — forming the primary in-line yield monitoring feedback loop that drives corrective action in high-volume semiconductor manufacturing.
The Core Challenge: Signal vs. Pattern
Bare wafer inspection operates against a featureless silicon background. Patterned wafer inspection must find a 30 nm particle or a missing via among billions of intentional circuit features — the signal-to-noise problem is fundamentally different and far harder. The solution is image subtraction: compare what is there against what should be there, and flag the differences.
Comparison Algorithms
Die-to-Die (D2D) Comparison
The inspection tool captures images of adjacent identical dies on the same wafer and subtracts them pixel by pixel. Features that appear identically in both dies (intentional circuit) cancel to zero. Features present in one die but not the other (defects) survive subtraction and are flagged.
Strength: Fast, sensitive to random defects, no reference database needed.
Weakness: Misses "repeater" defects — defects that appear on every die identically (reticle defects, systematic process problems) because they subtract out.
Die-to-Database (D2DB) Comparison
The inspection tool renders the GDS II design database (the photomask blueprint) into a reference image and compares each scanned die directly against this computed ideal. Every deviation from the design intent is flagged.
Strength: Catches repeater defects and systematic process errors. Enables absolute pattern fidelity assessment.
Weakness: Slower, computationally intensive, requires accurate database rendering, sensitive to process-induced CD variation that creates false alarms.
Hybrid Strategy
Production lines typically run D2D for high-throughput monitoring and D2DB for reticle qualification, new process node bring-up, and systematic defect investigation — complementary approaches covering different failure modes.
Critical Layers and Sampling Strategy
Not every layer is inspected 100% — throughput and cost constraints require sampling. Critical layers (gate, contact, metal 1, via 1) receive full-wafer inspection on every lot. Less critical layers use skip-lot or edge-only strategies. The sampling plan is tuned based on historical defect density, layer criticality, and process maturity.
Tool Platforms: KLA 29xx/39xx optical inspection; ASML HMI e-beam inspection for highest resolution at advanced nodes where optical tools can no longer resolve sub-10 nm defects.
Patterned Wafer Inspection is spot-the-difference at nanometer resolution — automated image comparison running at throughput of 100+ wafers per hour, finding the one broken wire or missing contact among ten trillion correctly formed features that determines whether a chip works or fails.