Wafer Inspection Methods are the comprehensive suite of imaging and detection technologies used to identify defects, particles, and pattern anomalies on semiconductor wafers during manufacturing — combining optical microscopy, electron beam scanning, and automated image analysis to detect defects as small as 10-20nm at throughputs of 100-200 wafers per hour, enabling yield learning and process control across all fabrication stages.

Optical Inspection Systems:

• Brightfield Inspection: illuminates the wafer surface with white or monochromatic light and captures reflected images using high-NA objectives; detects surface defects, particles, and pattern variations by comparing die-to-die or die-to-database; KLA 29xx series achieves 20nm defect sensitivity at 200 wafers/hour throughput on 300mm wafers
• Darkfield Inspection: uses oblique illumination angles (45-85 degrees) to scatter light from defects while the patterned surface reflects specularly away from the detector; extremely sensitive to particles, scratches, and surface roughness — detects sub-20nm particles that are invisible in brightfield mode
• Multi-Mode Inspection: combines brightfield, darkfield, and multiple wavelengths (UV 193nm, DUV 266nm, visible) in a single tool; different defect types have unique optical signatures across modes — particles scatter strongly in darkfield, pattern defects show contrast in brightfield, residue appears in specific wavelength channels
• Patterned Wafer Inspection (PWI): scans patterned wafers after lithography, etch, or deposition; compares each die to a reference (golden die or design database) using normalized cross-correlation; flags deviations exceeding threshold as potential defects; Applied Materials PROVision and KLA 39xx series dominate this segment

E-Beam Inspection:

• Scanning Electron Microscopy (SEM): focused electron beam rasters across the wafer surface; secondary electrons emitted from the sample form high-resolution images with <2nm resolution; critical for sub-10nm defect detection at advanced nodes (5nm, 3nm, 2nm) where optical wavelengths cannot resolve features
• Multi-Beam Inspection: uses arrays of 9-196 parallel electron beams to increase throughput 10-100× over single-beam systems; Hermes MBMV and Applied Materials SEMVision G7 achieve wafer-scale inspection in reasonable timeframes despite electron beam's inherently slow scanning speed
• Voltage Contrast Inspection: detects electrical defects (open circuits, shorts) by imaging charging differences; defective structures charge differently under electron beam exposure, appearing as bright or dark regions; identifies electrical failures invisible to optical inspection
• Review SEM: high-resolution follow-up inspection of defects flagged by optical tools; provides detailed images for defect classification; Hitachi and AMAT review SEMs achieve sub-1nm resolution for root cause analysis

Macro Inspection:

• Full-Wafer Imaging: captures entire 300mm wafer in a single image or stitched mosaic using low-magnification optics; detects large-area defects (scratches, stains, edge chipping, backside contamination) and wafer-level patterns (radial gradients, center-to-edge variations)
• Edge Inspection: specialized systems inspect the wafer bevel and edge exclusion zone where handling-related defects concentrate; edge defects can propagate inward during subsequent processing, causing yield loss in die near the wafer periphery
• Backside Inspection: inspects the wafer backside for particles and contamination that can transfer to process equipment or the wafer frontside; critical for preventing cross-contamination in cluster tools and lithography scanners
• Defect Detection Algorithms: die-to-die comparison aligns and compares adjacent dies; die-to-database compares to rendered design; machine learning classification using CNNs reduces false positives by 50-80%; KLA and AMAT integrate ML into inspection tools

Wafer inspection methods are the eyes of the semiconductor fab — detecting the invisible defects and process variations that would otherwise destroy yield, providing the data foundation for defect density reduction, process excursion detection, and continuous yield improvement that enables economic production of billion-transistor chips.