Wafer-Level Packaging (WLP) is the packaging technology where the chip is packaged while still in wafer form, with solder bumps and redistribution layers (RDL) formed directly on the wafer before dicing — eliminating the traditional die-level packaging steps (wire bonding, molding) to produce the smallest possible package footprint, lowest cost per package, and best electrical performance for mobile, IoT, and high-performance applications.

WLP Types

Fan-In WLP

• Bumps placed directly on the die — package footprint equals die footprint.
• Process: Deposit passivation → pattern UBM (Under Bump Metallurgy) → plate solder bumps → dice.
• Simplest and cheapest WLP — no substrate, no molding.
• Limitation: IO count limited by die area (bump pitch ~0.4-0.5 mm).

Fan-Out WLP (FOWLP)

• Die embedded in epoxy mold compound → RDL extends IO beyond die edges.
• Package larger than die → more bumps than die area alone allows.
• TSMC InFO (Integrated Fan-Out): Key technology for Apple A-series processors.

FOWLP Process Flow

1. Known Good Die (KGD): Test wafers, dice, select good dies. 2. Reconstitution: Place dies face-down on carrier with precise spacing. 3. Molding: Epoxy mold compound fills between dies — forms reconstituted "wafer." 4. Carrier release: Remove carrier — expose die front faces. 5. RDL formation: Deposit and pattern Cu redistribution layers (lithography + plating). 6. Bump formation: Plate solder bumps on RDL pads. 7. Singulation: Dice individual packages from reconstituted wafer.

RDL (Redistribution Layer)

• Copper traces that re-route die IOs from their original positions to a standard ball grid.
• Fine-pitch RDL: Line/space 2/2 μm (TSMC InFO) to 5/5 μm (standard FOWLP).
• Multiple RDL layers enable complex routing — 3-5 layers for high-IO chips.
• RDL quality (resistance, reliability) critical for package-level signal integrity.

Advantages of WLP

• Size: Smallest possible package — critical for smartphones, wearables.
• Cost: Batch processing at wafer level — no individual die packaging.
• Electrical: Short interconnect paths → lower inductance, better high-frequency performance.
• Thermal: Thin package → better heat dissipation to PCB.

Advanced WLP Applications

• TSMC InFO: Apple iPhone processors since A10 (2016) — FOWLP with high-density RDL.
• InFO-PoP: Package-on-Package with DRAM stacked on logic — mobile AP standard.
• Chiplet integration: FOWLP enables heterogeneous die integration — multiple chiplets in single package.

Wafer-level packaging is the dominant packaging technology for mobile and consumer electronics — by performing all packaging steps at wafer level, it achieves the smallest form factor and lowest cost that the smartphone and IoT industries demand, while providing the electrical performance needed for multi-GHz wireless communications.